A microprocessor based E.E.G. recorder was designed and partly built. The main purpose of the machine was that of a variable length delay line to permit the capture of up to 5 seconds of pre-trigger information with a 500Hz sampling rate and 16 analogue channels.
The large number of digitised samples to be stored dictated the use of dynamic semiconductor memory, with its attendant low cost, power and physical volume. The microprocessor was used to control the flow of data because this was more versatile and easier to implement than separate counter. the microprocessor communicates with the user and peripheral machines via an easy to use command driver program.
The complete construction of the recorder was prevented by persistent errors in the dynamic memory, by elimination of possible faults, and the nature of the errors, the cause was deduced to be crosstalk between data lines. This is a fault in the physical construction, the prototyping system used not permitting a compact layout.
The design of the interfacing logic was fundamentally correct, with only one minor fault which did not account for the observed errors.
The recorder will have to be reconstructed providing an opportunity to simplify and correct these problems, possibly using a better microprocessor.
1.0 Introduction
1.1 Specification
2.0 Report
2.1 Dynamic memory technology
2.2 Dynamic RAM operation
2.3 Refreshing needs
2.4 Choice of Microprocessor
2.5 Design choice
2.6 Design approach
2.7 Memory organisation
2.8 Refreshing method
2.9 Control signal generation
2.9.1 Row Address Strobe and ROW/!COLUMN Select
2.9.2 Early Write
2.9.3 Memory mapping
2.9.4 WR, RD and IO/!M regeneration
2.9.5 Direct transfer controls and DRAM buffering
2.9.6 CAS Enable
2.9.7 Refresh signal
2.9.8 Column address strobes CASH and CASL
2.9.9 The data converters
2.9.10 The non volatile RAM
3.0 The Software
3.1 The delay method
3.2 Post trigger countdown
3.3 The Command driver program
3.4 The Interrupt handler program
3.5 Modifications to the Q-Bug Monitor
4.0 Results - The non volatile RAM
4.1 Results - The DRAM interface
5.0 Conclusions
6.0 Appendices
6.1 Resets and Restarts
6.2 Modifications to Q-Bug Monitor
6.3 Interrupt handler
6.4 Command address look-up table
6.5 Command driver program
6.6 Memory map
6.7 I/O map
7.0 List of ICs
8.0 References
In many experiments where a unique event is to be recorded, a suitable trigger does not occur until after the start of the event and so pre-trigger information is lost. It is wasteful to record continuously and hope the event occurs before the recording medium is exhausted - especially when the event cannot be predicted.
A better solution is to record the delayed event when the trigger occurs, thus capturing the event effectively as it was in the past. The advantage is that the event may happen at any time.
Professor D.M. Mackay of the department of Communication and Neuroscience, is currently studying the response of areas of the brain to complex stimuli. For instance, an assistant watches a simple video game in which a target moves from left to right. Pressing a trigger fires a missile along the centre of the screen with three possible results; miss early, hit or miss late.
In this experiment, not only is pre-trigger information required, but several recordings must be averaged to improve the signal to noise ratio by a factor of root N where N is the number of recordings taken.
The signal is the response to the stimulus, and the noise is caused by the brain's other activities. Only a fraction of the brain is devoted to handling the stimulus so the observed signal to noise ratio is approximately 1 part to 10. Typically, 100 recordings are needed to obtain a 1 to 1 S/N ratio. It is important to note that averaging is a valid noise reduction technique only if the noise is of uniform distribution throughout the frequency range. Low frequency and 1/f noise would adversely affect the results.
At present, an Alpha minicomputer is used to average the records and store the results on magnetic disks. the delay line consists of ten sets of shift registers 1024 bits long. The digitised samples are shifted from the Analogue to Digital Converter (ADC) to the Digital to Analogue Converter (DAC) at a rate determined by the clock speed.
The present arrangement is shown in Fig. 1. There is a great deal of redundant circuitry, but the main disadvantage is the nature of the digital delay. The delay time can only be increased by reducing the sampling rate. The delay times obtainable at an acceptable sampling rate are proving inadequate.
By using a random access memory, the data could be read out at any point in the memory, creating a variable length shift register. The delay time can then be varied independently of sampling rate. Random access memories used in computer are readily available with higher capacities. The largest common chips available contain 65536 bits in a 16 pin package.
In using random access memory (RAM), several counters are required to remember where the data must be written to and read from. A microprocessor can handle this task and also communicate with the user.
This report deals with a design based on the Intel 8085A microprocessor, and the 4164 dynamic RAM. For the benefit of others wishing to continue this project, a detailed review of several popular microprocessors is included outlining their individual advantages.
A novel aspect of this design is the ability to pass 16-bit data words directly to and from the converters without having to pass the data via the microprocessor which can only transfer 8 bits of data at a time. Although this approach does speed up the data handling, the increase is negligible in comparison with the time needed to update the various address pointer. With hindsight this facility was not essential.
the memory was organised in 16-bit wide words to allow this direct transfer of 16-bit words and leave the option open of using a processor with a 16-bit data bus.
The construction of the converters was left till last because the design only allows data transfer via the DRAM, and Professor Mackay is familiar enough with converters to complete the project if lab. time expires. The implementation of converters is a simple task due to the wide variety single-chip converters available.
The original requirement specified a maximum delay of 5 seconds. the maximum frequency of interest is 200Hz therefore the Nyquist theorem indicates a sampling frequency of approximately 500Hz. With 16 channels the total number of words required is:
16 x 5 x 500 = 40,000 words
and the actual conversion rate is
16 x 500 = 8000 conversions per second
requiring one conversion every 125 microseconds. Furthermore, each conversion must be at least 10-bit accuracy because the main purpose is to show the relative amplitude of responses of different areas which often differ by a factor of ten or more.
Semiconductor read/write memory (hereafter referred to as random access memory or RAM can be divided into two general groups:
1) Static RAM (sRAM) in which the individual memory element is a transistor bistable. The state of the element remains unchanged until deliberately altered. The disadvantage is that power must always be used to bias the several transistors. Higher bit densities can be obtained by using larger scale integration but the higher power densities would produce unacceptable temperature increases without extra heat sinking. CMOS technology uses less power than common NMOS chips, but 2K by 8-bit (16 Kbits) is the present economical limit.
2) Dynamic RAM (DRAM) in which the data are stored as the presence or absence of charge on the gate capacitance of a MOSFET transistor. Originally the gate capacitance of bistables allowed certain elements to be omitted, but present technology only requires a single transistor and capacitance.
The advantages are higher bit densities not just because the memory elements require less area on the silicon die, but also because of the lower power consumption. The only current consumed by the element is the leakage current of the capacitors.
The disadvantage is that the charge on the capacitors must be periodically refreshed. Although silicon dioxide is an excellent insulator, the capacitors are necessarily small, and the refresh period is typically 1 to 4 milliseconds. Also, the architecture of DRAMs requires time-critical control signals and more complicated addressing. These problems are only worthwhile solving if large memories are required (in practice more than 8K by 8 bits).
Most DRAM chips use a multiplexed address bus where two separate sections of the binary address are placed on one set of pins and latched internally, but at different times. This technique is most appropriate to the internal organisation of DRAMs, but also has the advantage of reducing the number of address lines and hence the size of the final package.
The data sheet of the 4164, a 64K by 1 bit device, does look formidable and deters many into leaving DRAMs to professional designers. In fact, DRAMs are quite versatile in operation and the data sheet is merely a thorough attempt to define the limitations. there are several modes of operation, the simplest of which is outlined below for the 4164:
i) The eight row address bits are set up on MA0 to MA7, remaining on and at least 20 ns after the falling edge of the Row Address Strobe (!RAS) which operates the internal edge-triggered latch.
ii) The eight column address bits are set up on MA0 to MA7, remaining on and at least 45 ns after the falling edge of the Column Address Strobe (!CAS) which operates another internal edge-triggered latch.
Data on the data input pin (D) must be valid on and at least 45 ns after the falling edge of the CAS during a write operation. Data is valid on the data output pin (Q) 100ns after the falling edge of the CAS or 150ns after the falling edge of !RAS, whichever is latest, during a read operation.
The write enable pin (!W) dictates which of the two above operation occurs. !W is low during writing and high during reading. If !W is valid on and during !CAS low, the D and Q pins can be wired together to become a common data input/output as is the practice with most if not all common microprocessors. This mode of operation is called the Early Write mode.
!CAS also acts as a chip select pin, the data output pin being in the high-impedance (Hi-Z) state while !CAS is high.
The individual memory elements are organised as a square array of 256 rows by 256 columns. Every row address strobe refreshes the appropriate charge on every capacitor on the single row addressed. Every column address during a read operation uses the charge on a single capacitor to drive sense amplifiers and the data output pin. because the charge is shared with the sense line capacitance, each read operation refreshes all but the accessed capacitor on the single row accessed.
Every capacitor must be refreshed every 4 ms to avoid data loss. There are many ways of satisfying this requirement, some suitable for specialised machines such as framestores, some only suited to particular microprocessors.
In brief, refreshing must be done at a time when the microprocessor does not need to access the DRAM. This is known as transparent refresh because the microprocessor is unaffected and behaves as though it were accessing a static RAM. There are available "intelligent" DRAM controller chips which can instruct the microprocessor to wait, while a refresh operation is carried out, if sufficient refresh operation are not granted. Such chips are usually expensive, and only produce not entirely transparent operation.
The ease with which DRAM can be interfaced depends very much on characteristics particular to the microprocessor used (hereafter referred to as the CPU, an abbreviation of Central Processing Unit).
A wide variety of CPUs exist but although there may be one ideally suited to the application, it may not be worth time and effort to find relevant technical information if the device is uncommon (and usually expensive).
Choice was limited to four CPUs for high information is abundant by virtue of their use in personal computers (the 6502, Z80A and 6809) or long use in industry (the 8085A).
a) The 6502
The regularity of memory accesses makes implementation of shared memory extremely easy. The 6502 may take turns to access memory with another device to refresh DRAM, access video display data, or even a second processor.
Commercial DRAM interfaces are usually full of poor design practices (e.g. Audio Computers' 64K DRAM for the Acorn Atom) and magazine designs unnecessarily complex (see all magazine references). A very simple yet versatile DRAM interface for the 6502 has been built as a T2 project (Howell, K.M.R, unpublished).
The instruction set for the 6502 is mainly oriented to operating upon memory directly. The 6502 has eight flag bits, an eight bit accumulator A, and two eight bit registers X and Y used mainly for indexing.
This architecture is well suited for high level languages such as BASIC where many variables are stored in memory, but when handling a few variables only, the CPU is slowed by having to store them in memory inbetween instruction. there are no 16-bit handling instructions.
b) The 6809
The 6809 has all the advantages of the 6502 plus a more powerful and well ordered instruction set containing 16-bit handling instructions. The 6809 has two 8-bit accumulators A and B which can be used as a single 16-bit accumulator D, two 16-bit index registers and two 16-bit stack pointers. Two 'standard' disk operating systems exist: Flex and OS9.
Despite being the most powerful CPU being considered, its late market arrival prevented widespread popularity and consequently information is relatively scarce.
c) The 8085A
The 8085A contains three 16-bit register pairs and a limited number of 16-bit instructions. These include increments, decrements, addition, and stack operations. The register pairs can be used as memory address pointers which is well suited to this project. The instruction set is rather irregular and not all register pairs can be used in the same manner.
The biggest disadvantage is the multiplexed data bus. The least significant address lines are also used to transfer data, which creates bus timing hazards to avoid when using chips outside the 8085A family.
Although relatively old, the 8085A varies greatly in price as manufacturers move to more advanced processors.
d) The Z80A
This CPU can be regarded as a high-performance upgrade for the 8085A and 8080 CPUs. The Z80A will run all 8080 and 8085 machine code apart from RIM and SIM, two seldom-used instructions. A complete alternate set of registers can be used for fast interrupt response from within a currently running program. Two new 16-bit indexing registers X and Y have been added.
There are more interrupt modes and a more powerful easy-to-use family of support chips, notably a counter/timer chip, a peripheral input/output chip, and a dual asynchronous receiver/transmitter. Widespread use in microcomputers has lead to the Z80A family being extremely cheap (less than £4 each).
The bus is non-multiplexed, and the CPU contains circuitry to refresh DRAMS while decoding instruction. the bus control signals are much simpler although this can have disadvantages. A Z80 cross-assembler (Hawksley, C, 1979) is available on the university's 4082 mainframe, which supports labels, pseudo op- codes, memory reservation, byte and 16-bit word definitions. Programs can be stored as a file, assembled into absolutely addressed code, and down-loaded via the printer port of any terminal in the Physics department.
The data sheet produced by the designers (Zilog Inc.) is not encyclopaedic, so some design questions will have to be answered by experiment. An important example being "does !RFSH go low before !MREQ, in order to select an external refresh-row address counter?". This is because the internal refresh row counter is only 7 bits long and so only capable of refreshing 127 rows.
the Z80A was the preferred choice for it simpler data bus, large register set, and high-performance support chips. Construction as a stand-alone system was desirable to simplify memory addressing and buffering.
At the start of the time allocated, only two machines were available. The 6502 based Acorn Atom with 256x192 graphics, BASIC, assembler, user EPROM socket and tape interface. the 8085 based Quarndon system has a line assembler/disassemble, and most importantly RAM from location zero which allows the user to directly program the reset, restart and interrupt vectors. Had the disk interface been working, the CP/M operating system would allow many useful commercial programs to be run such as BASIC, assemblers and debugging tools.
The 8085A, being the second best solution was chosen. The Quarndon system imposes several restrictions:
i) There are no control lines by which the RAM and ROM on board the CPU card can be disabled by other cards on the mother board. This means that address decoding must be more complicated than necessary to avoid bus arguments.
ii) Not all 8085A signals are present on the Quarndon bus (Q- bus). Additional circuitry must regenerate these if needed.
iii) Having to drive the high capacitance of the Q-bus requires the use of extra buffers.
iv) The extra delays introduced by the above problems causes signal timings to differ from those guaranteed in the 8085A data sheets.
Like most other 8-bit CPUs, the 8085 is limited to a 16-bit address bus and hence a 64K (=65536) addressing range. The minimum memory required is 40000 by 10 bits which is not convenient for a CPU that can only read 8 bits in one access. The memory must be organised to appear as 80000 by 8 bits to the CPU. Most memory devices fully utilise the address space allowed by the number of address lines allocated and so come in capacities of 2^n where n is the number of address lines. Hence 80000 locations require an addressing range of 128K.
Paging is a technique by which an output port provides some of the extra address lines to specify which section of the memory appears in the memory map of the CPU. By allowing one page per channel, the 128K memory could be divided into 16 pages of 8K.
The software was investigated next to determine whether the CPU would be able to handle interrupts in the 125 microseconds available. The Z80A has special instructions to exchange it alternate register and so handle interrupts with minimum disturbance to a program running in the normal register set. The original intention was to use 8085A instructions to simulate the Z80A exchange instructions so the 8085A could handle interrupts whilst running a program.
This was thought to be of benefit because the CPU could average the previous recording while continuously servicing interrupts. This would allow triggers to be accepted at any time because the delay line would always contain valid data.
In practice this feature would not be needed. If being used as a delay line, the CPU would have no other tasks to perform after the initial loading. If being used to average results as well, the delay line and interrupts would have to be stopped to prevent the valid record from being overwritten by new data. In both cases the CPU is able to devote all its tie to waiting for interrupts.
Unfortunately this point was overlooked in the initial stages and two interrupt handlers were written. the first used the stack pointer to exchange the registers with memory in the fastest possible way. The second only used the normal registers initialised by the driver program and waited for the next interrupt, only jumping to the averaging program after all the post trigger data had been collected.
The worst case response times were calculated to be 127 microseconds and 67 microseconds respectively.
The most complicated solution was attempted for several reasons. Firstly it was felt that a dedicated machine would be a great improvement over an add-on machine for a microcomputer. Secondly the machine itself puts a limit beyond which no amount of clever programming will improve performance.
Previous experience of DRAM showed that the timing requirements to be not difficult to satisfy, and no great problems were anticipated.
The DRAM was constructed as 64K by 16 bits to allow the data word from the converters to be transferred directly. The CPU reads the least significant 8 bits on the even-numbered addresses, and the most significant 8 bits on the odd-numbered addresses.
Since the 8085A does not indicate when the memory may be refreshed during the processor cycles, the only time the DRAM is available for refreshing is when the CPU is accessing a different area of the memory map. This will be most of the time because the DRAM is only used as a data store.
The only limitation is that the CPU must make at least 256 accesses, to memory other than DRAM, every 4ms. Assuming an access takes 1 microsecond (as it does for an 8085A with a 3MHz clock) then the DRAM is available for:
( ( 4000 - 256 ) / 4000 ) * 100% = 93.6% of the time
The only way the CPU uses memory for more than 93.6% of the time is when the program is being run in that memory.
All times refer to minimum values unless marked otherwise
All timings in nanoseconds
The design of most DRAM interfaces starts with careful scrutiny of the timing diagrams of both CPU and DRAM chips. The reader is referred to Figs. 2 and 3 for a simplified view of the timing outlining the major requirements, but extensive details are given in the manufacturer's data sheets. The control signal circuitry is shown in Fig. 5.
i) Early Write and regenerated controls
ii) !RAS and ROW/!COL select
iii) DRAM controls and buffer enables
ALE, the address latch enable, is the most important control signal in the 8085A. It marks the start of every access, latches the least significant 8 address lines, and most other timings are referenced to the falling (negative) edge of ALE. All address lines are guaranteed valid at least 100 ns before, and 100 ns after this edge. The minimum width of ALE is 140 ns. ALE can thus be used directly as !RAS.
The row address need only be valid for 20 ns after the falling edge of !RAS so if !RAS is put through a small delay (an RC network and a Schmitt trigger is sufficient) the delayed !RAS can be used as the ROW/!COLUMN select for the address multiplexer. The RC time product should only be used as a rough guide to the time tdelay, particularly with ceramic capacitors. Experiment showed a 100 Ohm resistor and a 680pF capacitor to give an adequate delay of 40ns.
When the 4164 is used with D and Q commoned, !W must be valid throughout !CAS low. The 8085A has two very useful signals, S0 and S1, which give advance status of the access being performed.
S1 S0 Access status
0 0 Halt
0 1 Write
1 0 Read
1 1 Instruction fetch
The write status is detected and used as the early write control !W. !W is then inverted to produce the Receive/Send control (R/S) for the data buffers.
The most significant address lines, and the regenerated IO/!M signal,are sent to the inputs of a 74LS138 one-of-eight decoder. The 74LS138's output are used to select one of four input/output areas, and are directly connected to the output enables of the data buffers and chips being accessed. All the output enables are active low.
These are three 8085A signals which do not appear on the Q-bus. !WR and !RD are needed for the 2K of non-volatile RAM (described later) on board the prototyping card.
The CPU has an output E which goes low if !RD, !WR or !INTA go low. The Quarndon manual states that E goes low to effect the data transfer after the address and data lines have
M is inverted on the CPU card to become IO/!M. IO/!M merely requires another inversion before being used by the 74LS138 decoder.
All the gates used to regenerate !WR, !RD and IO/!M are intentionally located on the same chip, so that the addition of an on-board CPU would only require the removal of the chip from its socket without needing re-wiring.
When the CPU is accessing the DRAM, only half of the 16-bit word can be accessed at a time, so these accesses are detected by half of a 74LS139 dual one-of-four decoder to enable the high or low byte data buffer.
During a direct memory transfer, neither data buffer is enabled. The CPU provides the address to the DRAM as normal, but the converters provide or receive the appropriate data. Both the high and low byes are accessed, and the other half of the 74LS139 detects the direct transfers and either reads the analogue to digital converter (ADC) or writes to the digital to analogue converter (DAC). Note that the DAC is written to when the DRAM is being read, and the ADC is read when the DRAM is being written to.
An extra input, not previously mentioned, is needed to indicate whether a CPU access or direct memory access (DMA) is to occur. This input can be provided by an output port or an address line. If a memory device is selected which is smaller than the memory area allocated, the entire contents of the device appear several time within that area. These duplicated locations are termed echoes. By accessing a particular echo one can indicate the transfer required using an unused address line. The advantage is that no input/output (I/O) port need be used. Unfortunately the DRAM is not echoed, in this design, to avoid argument with the Quarndon memory.
This is an important intermediate signal. CAS Enable (CASEN) goes high if !WR, !RD or !INTA go low. In this respect CASEN can be regarded as the inverted equivalent of the Q-bus signal E.
When the DRAM is not being accessed, the DRAM area select (pin 13 of the 74LS138) is high. This indicates that the DRAM may be refreshed. The DRAM area select is inverted to drive the refresh row output enable (!RROE) of the multiplexer circuit. This places the refresh row address on the multiplexed address bus (MA0-MA7) throughout the access and is latched into all the DRAM chips by RAS.
The refresh row counter is incremented on the high-going edge of CASEN. The counter may only increment after a refresh row has been latched in, to avoid any rows being missed. Although it is unlikely that the same row would be missed over a whole refresh period, it is a simple matter to halt the counter during CPU or DMA accesses. CASEN is NANDed with the DRAM area select to provide the negative edge-triggered refresh row clock (RRCLK).
At the start of the project it was thought that a 16-bit wide memory would only require the use of a single column address strobe. Whilst this is true for DMA reads and writes and CPU reads (the latter because the buffers only select one byte of data) this is not the case for CPU writes, which would write garbage into half of the 16-bit data bus.
In practice this complicates matters by requiring two separate column address strobes, only one of which is active during a CPU access, but both are active during a DMA access. This problem was solved by using the data buffer output enables to disable the appropriate column address strobe.
If neither data buffer is enabled during a DRAM access, then a DMA transfer is occurring and both column address strobes high and low (!CASH and !CASL respectively) are enabled. If the high buffer is enabled, this disables !CASL. Likewise the low buffer enable disables !CASH.
Single-chip data converters are readily available, usually with TTL compatible control and outputs. However, increasing accuracy requires finer tolerances on the analogue internal components. Cost increases rapidly after about 8 bits accuracy. Although 10- bit accuracy was specified, a 12-bit ADC was available from a previous project which helped reduce project costs.
The ADC574 is and ADC with several modes of operation and only five control pins.
Pin 2, the data mode select, controls whether the data is read 12 bits simultaneously (when tied high) or 8 bits in two addresses (when tied low). In this project pin 2 was tied high.
Pin 3, CS, is an active-low chip select. This pin was tied low.
Pin 4, A0 is used to control whether the high or low data is read in the two-address mode. As this mode was not used, the state of A0 was unimportant. A0 also controls whether a full 12-bit or 8- bit conversion is performed. A0 was tied low to initiate the full 12-bit conversion.
Pin 5, Read/Convert, goes low to start the conversion and is high during reading. This pin is connected to an output port so the CPU can read or start conversions from software.
Pin 6, CE, is an active-high chip enable. This pin was tied high. Because the chip is permanently enabled (!CS= 0, CE = 1) the digital outputs are valid while Read/Convert is held high. This is no problem because the output are buffered by a pair of 74LS244 unidirectional tri-state buffers. The AD574 has tri-state outputs, but is not capable of driving the 16-bit data bus directly.
Pin 28, Status, goes high to indicate the completion of a conversion. This output was not used, as the CPU can be sure that the 12-bit conversion (taking 35 microseconds maximum) will be completed in the 125 microsecond minimum sampling time available.
The DAC used was the AD5745. It was chosen and ordered because it could accept a 12-bit word and was internally latched, but no further time was invested because the use of the CPU as the averager would have removed the need for this facility.
A HI506 one-of-sixteen analogue multiplexer was chosen because the multiplexer of the cheaper 4000 CMOS series had a crosstalk of -50 dB. To keep crosstalk below one least-significant bit, 10-bit accuracy requires better than -60 dB and 12-bit accuracy requires better than -70 dB.
With no disks or tape interface, the only way to save programs was on the EPROM programmer. Machine code programs were required to handle the interrupts sufficiently quickly, and communicate with the user. The interrupt handler is sufficiently short to type in by hand, but the communication program was extremely long (approx. 700 bytes) and would be very tedious to retype. The EPROM programmer takes five minutes to backup a program, which is acceptable at the end of a programming session, but when testing a machine-code program any errors usually result in the program corrupting itself. Program backup every time a new section of code is tested would be time consuming.
RAM made with CMOS technology uses very small stand-by currents, so a small battery can be used to retain data for considerable periods. The 6116 is such a RAM, and has a pinout similar to the 2716 EPROM, which lends itself to the purpose of short program storage. A small device was made to simulate a 2716, and fit in the 2716 socket provided on the prototype used.
This consists of a 6116 static RAM with write-protection and battery back-up. The simulator is on a small printed circuit board and plugs into a 24-pin socket.
When power is applied to pin 24, the simulator behaves as a normal 6116. Programs can be written, read, and run using up to 2K of memory.
A write-protect switch allows the user to prevent writing to the chip by holding pin 21 (!WR) high. the simulator behaves as a ROM, allowing programs to be run but preventing the program overwriting itself in the event of a crash.
Being a CMOS IC, stand-by current is approx. 1 to 10 microamps which is provided by a small 3.6V 100mAHr rechargeable battery. In this way data can be retained for about one year.
The CMOS inputs require pulling high or low, and the control inputs must be held high to keep the stand-by currents from exceeding 10 microamps.
The address and data lines would be pulled low by the unpowered chips also connected to these lines, but pull-down resistors ensure this when the simulator is removed from the host system.
A 4066 quad bilateral analogue switch isolates the active-low control signals from the plug so they can be pulled high.
While write is enabled, a red LED flashes to draw attention to the fact that the RAM is no longer write-protected.
This circuit is an improved and simplified version of published circuits in various magazines. The new aspect is that the circuit is transportable. The whole simulator can be removed from the host system and plugged directly into the target prototype.
The parameters of the delay line were to be implemented by software (programs). It is possible to write a program, in a high level language, to simulate a delay line but clever programming is required to implement the high sampling rate and large time delay needed in this application.
The data are written into consecutive locations on every interrupt. If the interrupt occur at intervals of dt, and the delay time required is T, then the data written T seconds ago is N locations distant from the present location where N = T/dt.
The method used is best explained graphically, taking the case of N = 5.
| location (M) | content | ||
| 5 | g | Initial state: M = N = 5 | |
| 4 | g | ||
| 3 | g | Contents all garbage (denoted g) | |
| 2 | g | ||
| 1 | g | ||
| 5 | <--g1 | d1<-- | First interrupt: g1 read out, d1 written in |
| 4 | g2 | ||
| 3 | g3 | Time = 0 | |
| 2 | g4 | ||
| 1 | g5 | ||
| 5 | d1 | Second interrupt: g2 out, d2 in. | |
| 4 | <--g2 | d2<-- | |
| 3 | g3 | Time = 1 dt | |
| 2 | g4 | ||
| 1 | g5 | ||
| and so on until: | |||
| 5 | d1 | Fifth interrupt: g5 out, d5 in | |
| 4 | d2 | ||
| 3 | d3 | Time = 4 dt | |
| 2 | d4 | ||
| 1 | g5<-- | d5<-- | memory pointer reset to N (=5) if zero is the next location. |
| The memory is now full of valid data when the sixth interrupt occurs: | |||
| 5 | <--d1 | d6<-- | Sixth interrupt: d1 out, d6 in |
| 4 | d2 | ||
| 3 | d3 | Time = 5 dt = T | |
| 2 | d4 | ||
| 1 | d5 |
d1 emerges from the memory T seconds after being written in, and hence is delayed. So too are all data written in.
A further refinement is to stop the delay line a fixed time after a trigger edge. This allows the CPU to stop when sufficient post- trigger data have been collected. If the post-trigger time is P, then the number of locations to be filled after the trigger is B where B = P/dt.
An additional counter C is loaded with B and only decremented when a post-trigger flag is set low. Taking the example where B = 2 and the flag is set on the seventh interrupt:
| location (M) | content | ||
| 5 | <--d1 | d6<-- | Sixth interrupt: d1 out, d6 in |
| 4 | d2 | ||
| 3 | d3 | B == 2 | |
| 2 | d4 | ||
| 1 | d5 | ||
| 5 | d6 | Seventh interrupt: d2 read out, d6 written in | |
| 4 | <--d2 | d7<-- | CPU sees post-trigger flag is set, |
| 3 | d3 | decrements B to 1 | |
| 2 | d4 | ||
| 1 | c5 | ||
| 5 | d6 | Eighth interrupt: d3 out, d8 in. | |
| 4 | d7 | CPU sees post-trigger flag is set, | |
| 3 | <--d3 | d8<-- | decrements B to 0, |
| 2 | d4 | therefore no more post-trigger data to capture, | |
| 1 | d5 | and the process stops. |
Obviously the final user would not like to load the parameters from the monitor every time. Apart from being slow, the monitor is not very easy to use. A relatively long program has been written to communicate, via the RS232 interface and terminal, with the user. 16 commands can be accommodated, and each announces its function before execution. A full disassembly is given, in the appendices, of the command driver program and also the interrupt handler.
on reset, the program initialises the stack pointer and disables interrupts before jumping to the initialisation routine. This prints the message:
Reset
before the command prompt appears:
Command _
Any valid hexadecimal digit (0 to 9 and A to F) will produce either:
Command Not implemented
Command _
or the digit command and its function. For example:
Command E - Exit
which exits the program and jumps to the Q-Bug monitor.
Other commands require a second digit, for example:
Command C - Change from 0 to _
which will use the second digit to select the page corresponding to that digit before returning to the command proper.
This is a relatively short program of about 40 bytes. It is located from 0038H even though the 8085A interrupt RST 7.5 begins at 0034H. This is to allow the program to run without relocation on the Z80A CPU which starts its maskable interrupt INT at 0038H.
There is no program for initialising the relevant counter. This would be a difficult program to write in machine-code because of the mathematics involved. The interrupt handler assumes that the counter are loaded already. A routine is required to halt the CPU and wait for interrupts after loading the counters. An interrupt will restart the CPU and will return with the zero flag set high if the end of the post-trigger data has been captured. Otherwise it will be reset low and the CPU must wait for an interrupt again.
Below is the programming model of the 8085A showing the names of the registers and their contents during interrupt handling.
| S Z X A X P N C | A | Flags, Accumulator |
| B | C | BC register pair |
| D | E | DE register pair |
| H | L | HL register pair |
| SP | Stack Pointer | |
| PC | Program Counter | |
| Flags, Accumulator: | general purpose main registers. |
| HL register pair: | Points to the memory location, M, to be read an
written to. |
| BC register pair: | Contains the number of interrupts to be handled before the end of the post-trigger data. |
| DE register pair: | Points to a look-up table in RAM containing the page
number to be used and the input number to supply the analogue data. |
The number of interrupt intervals to be delayed by (N) is contained in memory because no more registers are available.
The memory locations for storing the value of N in, and the locations for the page/input look-up table, have not been allocated yet. these location, and the data that will depend on the final hardware design, are denoted by asterisks.
The monitor contains several routines to drive paper tape punches. Although seldom used, they can be replaced by more useful routines. These exist at:
| Hex address | |
| FAB5 FAE8 |
DLRH : Read hex. format tape 51 bytes. |
| FB18 FB69 |
DLRP : Punch tape 81 bytes. |
| FB6A FB9A |
DLRR : Read Quarndon format tape 48 bytes. |
| FD71 FDD9 |
Various tape handling subroutines 104 bytes. |
DLRH is used to copy the non-volatile RAM down to the RAM at location 0000H.
This is a frequently needed operation
This worked correctly as previously described, when used on the prototyping board. When read by the EP4000 EPROM programmer, data appeared to be zero at every location due to the pull-down resistors. The output of the 6116 was not being enabled so there must be some minor difference in the output enable pins of the 2716 and 6116 chips. Further time was not spent on this problem because the main aim was to save time, in program back-up and program entry, which it did.
The DRAM interface did not work first time so the fault was traced in logical steps. The CPU appeared to successfully write to the DRAM but reading showed a very high error rate of about 50%.
A small test program was run (see appendix) to generate regular access type for observation with a 100 MHz bandwidth oscilloscope. no significant distortion was observed on any of the TTL driven lines, nor were there any reflected pulse.
All the control signals were active at the correct time (see Fig. 5) and within a single access cycle ALE, ROW/!COL , and CASEN satisfied their timing requirements (see Fig. 6).
The address multiplexer correctly selected the refresh row. the refresh row counter did halt during DRAM accesses and the logic state analyser verified the correct row was being latched in.
The test program observations showed no faults on the DRAM data outputs, and that the data out was the data being written in. Despite the apparently correct working of the addressing and controls, the DRAM persistently produced errors. The 8085A timing diagram was examined again to spot any fundamental timing faults in the read cycle.
Early on in the read cycle, before !RD goes low, the 8085A uses AD0-AD7 to output the lower address byte. The write status signal !W is high and indicates to the data buffers that data are to be output to the data bus. The 74LS138 always ensures one of the eight memory address areas is selected as soon as its address is valid, which is early in the access (typ. 10ns after ALE goes high) Hence a bus argument exists with the data buffers trying to force the low address to that of the data being read. Before !RD or !CASH or !CASL goes low, the outputs of the 6116 and the DRAM will be in the tri-state (high impedance or Hi-Z) condition and the buffers will see the data lines floating high and try to force the low address lines high. Symptoms of this fault would be the incorrect addressing of all locations except for those whose low address is FF hex, or all address in a 256-byte block accessing the same location and data when the low address is held to FF hex.
In practice these symptoms did not occur because of the low address being latched and the data lines being buffered on bard the CPU card. The 8T28 data bus buffer has a higher current output than the 74LS245 buffer so the former is not affected. The latched lower address is used to provide the row address for the multiplexer so these are also unaffected. The 74LS245 buffer recovers in time to work properly, as the correct data from the 6116 chip proves.
Since this minor timing design fault did not account for or cause any errors, the type of errors were looked at to find any clues to the cause of the fault. Here a high-level language would have been very useful for writing a program to analyse the errors in detail. in practice only a general analysis could be made.
A test program was written to flush the memory with all ones or all zeros. This was mainly to show that data written to a location only appeared once in the entire DRAM, but also to show that data were being stored. the results were initially encouraging with 94% to 100% of locations correctly reading back the data. Unfortunately any other data stored suffered an error rate of 50% at least.
Before risking eight expensive 4164s (£5 each!) the buffers were tested thoroughly. All locations appeared as FF hex, showing the data line floating high and that insufficient system noise was being picked up to pull any line low. Next each data line was shorted to ground in turn, showing the correct line was connected to the right data bit with no short-circuits.
Next a single chip was inserted and flushed with ones, which were all read back correctly. When flushed with zeros, other data lines went low as well on most accesses (90%). The data bit with the 4164 present seemed to be consistently zero so the other seven 4164s were added to see if the cross-talk would disappear.
The all-zeros or all-ones memory flush showed the individual data bits to be fairly reliable. The chance of a group of 8 bits all correct.
When data with a mixture of ones and zeros was written in, only 50% or less of a group of 8 bits were correct. This would imply a chance of a single correct bit to be 0.917, and the chance of a single wrong bit to be 0.083.
Because of the disagreement between the two calculated bit error rates, it is concluded that the assumption of statistical independence is invalid. Bit error were dependent on other bits. Cross-talk is the most likely cause of errors.
The less frequent errors when all zeros or all ones are written in can be attributed to electrical noise pick-up. Incorrect address multiplexing cannot be responsible because errors occur even when all addresses contain the same data.
The minor timing design fault is not responsible for read errors because it does not produce the pattern of errors expected.
In summary, the design of the whole machine is essentially correct although a simpler memory organisation would suffice. The errors are a result of the limitations of the prototyping boards used, which do not permit adequate compactness of construction (see photograph in Fig. 12)
The project will need reconstruction on a prototyping board permitting shorter interconnections. This will provide the opportunity to remove the read-access timing fault, simplify the circuitry and re-organise the memory as 8-bits wide.
The user may wish to move to using the Z80A CPU to make use of the computer centre's assembler or an adaptation of a suitable BASIC. Sinclair BASIC for the ZX81 is suited because the alternate registers, normally used for generating the video picture, will be freed for use. However, the screen handling and printer routines will need adapting to use a terminal. The Z80A support chips can now be used, but the DRAM interface must be re-designed because the control signals are different.
There is a CPU, the NSC800, capable of running the Z80A instruction set but having similar control signals and bus to the 8085A. An added bonus is an 8-bit refresh row counter and refreshing circuitry. The DRAM interface would require less alteration but the extra expense of the NSC800 may not be justified.
The simplest upgrade path would be to continue with the 8085A CPU, and write programs with the Z80A assembler taking care to use only the 8085A instruction subset. The 8085A is capable of performing the to the original specification, the only problem being the writing of a user-friendly program to load the parameters. A medium level language like FORTH may be suitable.
Note that where label names first occur, their hex values are quoted at their location. Values dependent on the final design are marked with asterisks. Only op-codes are printed, as in the Q-Bug monitor.
Op- Address Code Label 00 F3 DI : disable interrupts 01 31 LXI SP **** : initialise stack pointer 04 C3 JMP INIT : jump to start 07 00 NOP 08 C3 IVEC ; JMP ICHR : jump to input character 09 00 NOP 0A 00 NOP 0B 3E NXLN ; MVI A OD : print line feed code 0D FF RST 10 : by calling OVEC 0E 3E CRTN ; MVI A 0A : then carriage return 10 C3 OVEC ; JMP OCHR : jump to output character
FAB5 31 DLRH ; LXI SP FE7F : dollar H command FAB8 21 LXI H 4000 : boot program FABB CD CALL BOOT : from CMOS RAM FABE C3 JMP F810 : then Q-Bug ready FAC1 01 BOOT ; LXI B 0800 : move 2K bytes FAC4 11 DOWN ; LXI D 0000 : down to zero FAC7 7E LDIR ; MOV A A : transfers memory FAC8 12 STAX D : from FAC9 23 INX H : HL = source FACA 13 INX D : DE = destination FACB 0B DCX B : BC = number of bytes FACC 78 MOV A B : FACD B1 ORA C : BC = 0 ? FACE C2 JNZ LDIR : if no repeat FAD1 C9 RET : end
34 00 NOP : start of RST 7.5
35 00 NOP
36 00 NOP
37 00 NOP
38 3E HNDL ; MVI A, ** : set DMA flag an set
3A D3 OUT ** :
3C 7E MOV A, M : DMA
3D 77 MOV M, A : DMA
3E 1A LDA X D :
3F D3 OUT ** :
41 3E MVI A, ** : reset DMA flag
43 D3 OUT ** :
45 1C INR E :
46 7B MOV A, E :
47 FE CPI 10 :
49 CO RNZ :
LHLD **** :
55 DB CDWN ; IN ** :
56 E6 ANI 20 :
58 C0 RNZ :
59 0B DCX B :
5A 78 MOV A, B :
5B B1 ORA C :
5C C9 RET : and return with flag.
low high
byte byte Title
100 E2 O2 0 - Zeros
102 F3 02 1 - Ones
104 9C 02 2 Not implemented
106 9C 02 3 Not implemented
108 9C 02 4 Not implemented
10A 9C 02 5 Not implemented
10C 9C 02 6 Not implemented
10E 9C 02 7 Not implemented
110 9C 02 8 Not implemented
112 9C 02 9 Not implemented
114 45 03 A - Change INPUT from X to
116 9C 02 B Not implemented
118 52 03 C - Change PAGE from X to
11A 9C 02 D Not implemented
11C B2 02 E - Exit
11E 9C 02 F Not implemented
200 3A LPT LDA FE07 : Test format word 203 17 RAL : copied from Q-Bug 204 17 RAL 205 11 LXI D 208 D8 RC
209 11 VDU LXI D : Test terminal status 20C 1A LDAX D : Copied from Q-Bug 20D E6 ANI 08 20E C8 RZ 210 13 INX D 211 13 INX D 212 C9 RET
213 D5 ICHR PUSH D : Input character 214 CD CALL VDU : modified Q-Bug 217 1A LI LDAX D 218 1F RAR 219 D2 JNC LI 21C 13 INX D 21D 1A LDAX D 21E E6 ANI 7F 220 D1 POP D 221 C9 RET
222 D5 OCHR PUSH D : Output character 223 F5 PUSH PSW : modified Q-Bug 224 CD CALL LPT 227 1A LII LDAX D 228 E6 ANI 02 22A CA JZ LII 22D 13 INX D 22E F1 POP PSW 22F 12 STAX D 230 D1 POP D 231 C9 RET
232 7E TEXT MOV A, M : Print text string starting at M 233 B7 ORA A : modified Q-Bug 234 C8 RZ 235 FE CPI OD 237 CC CZ NXLN 23A C4 CNZ OVEC 23D 23 INX H 23E C3 JMP TEXT
241 E3 PRNT : XTHL : Print text following the 242 CD CALL TEXT : call PRNT instruction 245 23 INX H 246 E3 XTHL 247 C9 RET
248 CF HEX1 : RST 08 : Fetch character 249 D6 HEXT : SUI 30 : Test if valid hex 24B FA JM FAIL 24E FE CPI 0A : if valid 250 F8 RM : A = numeric value 251 FE CPI 11 : and sign value is minus 253 FA JM FAIL 256 D6 SUI 07 : if not 258 FE CPI 10 : A = ASCII code 25A F8 RM : and sign flag is positive 25B C6 ADI 07 25D C6 FAIL : ADI 30 25F C9 RET
260 3E INIT : MVI 87 : Initialise 262 32 STA FE07 : Format byte 265 21 LXI H FF02 268 36 MVI M 43 : and serial 26A 36 MVI M 51 : interface 26C 3E MVI A 03 26E D3 OUT F8 270 CD CALL PRNT 273 ascii #[CR] Reset# : ASCII string 27B 3E PMPT : MVI A F0 : light prompt LED 27D D3 OUT F9 27F CD RSET : CALL PRNT 281 ascii #[CR] Command# 28C CD CMD : CALL HEX1 : Fetch command 28F F2 JP CMD : valid numbers only 292 07 RLC 293 21 LXI H 0100 : address table 296 6F MOV L, A 297 5E MOV E, M 298 23 INX H 299 56 MOV D, M 29A EB XCHG 29B E9 PCHL : jmp to address
29C CD NIMP : CALL PRNT 29F ascii #Not implemented# 2AF C3 JMP PMPT
2B2 CD EXIT : CALL PRNT : Exit to Q-Bug 2B5 ascii #E - Exit CR# 2BD C3 JMP F810
2C0 01 ZERO : LXI B 0000 : Flush zeros 2C3 C3 JMP FLSH
2C6 01 ONES : LXI B FFFF : Flush ones 2C9 16 FLSH : MVI D, 0F : Flush 16 pages 2CB 72 LII MOV A D 2CC D3 OUT FA 2CE CD CALL PFLS : Flush one page 2D1 15 DCR D 2D2 F2 JP LII : Next page? 2D5 C9 RET
2D6 21 PFLS : LXI H 9FFF : Flush page 2D9 70 LIII : MOV M, B : from top down 2DA 2B DCX H 2DB 71 MOV M, C 2DC 2B DCX H 2DD AF XRA A 2DE 84 ADD H 2DF FA JM LIII 2E2 C9 RET
2E3 CD FLSZ : CALL PRNT : Title for zeros 2E6 ascii #0 - Zero# 2ED CD CALL ZERO 2F0 C3 JMP CMD
2F3 CD FLS1 : CALL PRNT : Title for ones 2F6 ascii #1 - Ones# 2FD CD CALL ONES 300 C3 JMP CMD
303 E6 CONV : ANI 0F : Convert accumulator 305 FE CPI 0A : low 4 bits 307 FA JM LIV : into ASCII code 30A C6 ADI 07 30C C6 LIV : ADI 30 30E D7 RST 10 : and print 310 C9 RET 311 4F CHLO : MOV C, A : change low 4 bits 312 E6 ANI F0 314 47 MOV B, A 315 CD CALL PRNT 318 ascii # from # : from present value 31F 71 MOV A, C 320 CD CALL CONV : on the screen 324 CD CALL PRNT 327 ascii # to # : to new value 32C CD LV : CALL IHEX : from terminal 32F FA JM LV 332 4F MOV C A 333 CD CALL CONV : and print 336 71 MOV A C 337 80 ADD B 338 C9 RET
339 0F CHHI : RRC : Change high 4 bits 33A 0F RRC : by swapping 33B 0F RRC : high 33C 0F RRC : with low 33D CD CALL CHLO : changing low 340 0F RRC : then 341 0F RRC : swapping 342 0F RRC : back 343 0F RRC : again 344 C9 RET
345 CD CINP : CALL PRNT : Change input 348 ascii #A - Change INPUT # 358 DB IN FA 35A CD CALL CHLO : on low bit 35D D3 OUT FA : of port 35F C3 JMP PMPT
362 CD CPAG : CALL PRNT : Change page 365 ascii #C - Change PAGE # 374 DB IN FA 376 CD CALL CHHI : on high bits 379 D3 OUT FA 37B C3 JMP PMPT
0000 to 05FF : 1.5K of Q-Bug RAM 4000 to 5FFF : 2K of non-volatile RAM 6000 to 67FF : EPROM programmer 2K RAM 6800 to 6FFF : EPROM programmer 1 or 2K EPROM 8000 to 9FFF : 8K page of DRAM EA00 to FFFF : Q-Bug monitor
F8 Control word F9 Port A FA Port B FB Port C input only on CPU card FC Timer low byte
IC1 74LS393 IC2 74LS244 IC3 74LS257 IC4 74LS257
IC5 74LS138
IC6 74LS139 IC7 74LS10 IC8 74LS132 IC9 74LS132 IC10 74LS14 IC11 74LS14
IC12 to IC28 4164
IC29 AD 574 IC30 HI 506 IC31 AD 5745
The specialised nature of the project meant a scarcity of useful data. Most was gleaned from data sheets or magazines. These are the most helpful or interesting:
| 4164 data sheet | Available from suppliers |
| 4416 data sheet | |
| 8085A data sheet | |
| Z80A data sheet | |
| Elektor Dec. 81 | Battery backed 6116 |
| Electronics and Computing Monthly April, May 84 |
Z80A machine code programs and circuits for using DRAMs as a simple imaging device or a printer buffer. Worth reading |
| Electronics digest: Vol. 4 No. 2 | Brief data sheets. Includes 6809, 8085, 6502 and NSC800 |
| Electronics and Computing Monthly August 82 |
Z80A machine code programs and circuits for using DRAMs as a simple imaging device or a printer buffer. Original source of battery backed 6116 idea. |
| Hawksley, C | A Z80 Cross-Assembler and Down-Line Loader for the
GEC 4082 Report No. 19, March 1979 |
I would like to thank those whose wit, wisdom sympathy and solder I borrowed or pinched during the project.