Designed by Bodo Wenzel using VHDL, and documented at Bodo's ZX97 page, this packs ZX81 functionality into a Xilinx XC3042. This device has more logic resources and I/O pins, allowing some improvements. Firstly properly multiplexing removed the need for the bus impedance resistors and their associated power consumption. Secondly an LCD interface was added.
The LCD part takes more than a third of the logic, as does the video part. You can't drop the video part, because the LCD logic just converts the video signal from a stream of 1-bit data to a stream of 4-bit data. It should be possible to drop the LCD logic if not desired.
Kai Fischer entered the circuit diagrams into the Eagle CAD package, and kindly sent me the circuit diagrams. Bodo does not have these on his site yet, and as far as I know this is the only site you can get them.
After developing the Xilinx design up to the point of passing the simulations, Bodo had not got time to make a PCB and so asked Kai to do so. This stage was shown at the 1998 ZX-Team meeting.
Prototype circuit (65K PNG)
Prototype image
The LCD interface and connector is patched on the free space. That's why the schematic doesn't match with the prototype and the VHDL sources.
After showing the prototype at the 1999 meeting Kai modified Bodo's design for his laptop LCD version. This uses a monochrome 320x240 pixel LCD display. It also includes flash memory. It requires and extra GAL20V8 and a few TTL chips. I'm told it doesn't drive composite video - yet! I suspect this just the LCD requires more scan lines than the 625 lines of a PAL video signal, and there is no simple way to select PAL pixel/line/frame rates from a link setting. This is a function of software and the NMI generator.
LCD Version circuit (227K PNG)
LCD Version photo (96K JPG)
VHDL project files
VHDL block diagram (sketch)
The laptop was shown at the 2000 meeting, and it is the picture at Bodo's ZX97 page. Kai asked whether it's possible to add the external ICs into the FPGA, but the design already almost fills the XC3042.
The extension was purely hardware, the FPGA was not extended. The simplest version would be to drop the extra memory chips from Kai's version, and change the VHDL for video output. The analogue parts (tape and TV) would also have to be adjusted for the user's needs.
I looked at Bodo's design and thought of building it with some added enhancements. As it stands, it is perfectly okay, but you still need a device to program the ROM that contains the configuration data and the system software. There's a way to do this without a PROM programmer: the JTAG interface allows systems to be tested by serial control of the component device pins, and if you have control over the pins connected to the PROM then you can program the PROM.
It's a great idea but it does require that the system has a JTAG interface, and the Xilinx XC3000 series chips don't have this. I had a look around for chips that do. Altera FPGA chips have JTAG but cannot program their own configuration PROMs in the way described above because they do not have a parallel address bus to the configuration ROM. They are clocked serial addresses with either 1-bit data or 8-bit data bus. This makes the programming and configuration processes slower.
Returning to Xilinx, their XC4000 series does have JTAG interfaces. The XC3042 in Bodo's design has a 12x12 array of logic cells. There is no direct equivalent of this size in the XC4000 series but the next one up is the XC4005 which has a 14x14 array. So I drew the XC4005 part and found it had fewer I/O connections than the XC3042. This is because more pins are devoted to power and ground (fourteen instead of four on the XC3042). Manufacturers do not give up I/O pins lightly so one can assume they found that they really needed more power pins. Certainly at high speeds it does become more important to have good power lines.
The final effect is that although moving to the next generation of Xilinx chips provides JTAG access and the XC4005 will provide more logic cells, there are fewer I/O pins. Thus upgrading this design is not as simple as changing the chip and adding a JTAG connector.
I'm sure there are ways round the I/O pin limitation, since the original Sinclair ULA fitted in a 40-pin chip. This involves a significant change in the logic and memory access requirements. This also allows it to fit in a smaller chip - Bodo also managed to clone the ZX81 in One Complex PLD and a few discretes. This used a 44 pin chip and so the LCD display is not supported.
I had a go at compiling Bodo's VHDL source using the Xilinx Webpack. This software does not support the 3000/4000 series chips (for that you need the Foundation series software). Perhaps reflects a desire by Xilinx to move on to more up-to-date chips.
The Webpack compiled it okay, and fitted it into a Spartan-2 XC2S15 chip in a 144-pin flat pack. The Spartan 2 series are not available in socketable PLCC84 packages. The earlier Spartan 1 has some PLCC parts but is being replaced by the Spartan 2 series.
I then tried to compile the VHDL design into a Xilinx CPLD These are easily reprogrammable unlike the MACH210, and VHDL is more portable and popular for high-level design. However I found that the only Xilinx CPLD parts containing enough logic and I/O only came in surface mount packages, so I was no better off.
I later found that the compiled design was demanding more I/O pins than expected. Eight pins to be exact, which pointed to a surplus data bus. I had seperate data in and data out buses. There was no file to instruct that they be joined. Bodo's source does this in the device-specific file zx97.vhd. I would need something similar for each target part. This might allow the design to fit in a PLCC packaged CPLD. If the amount of logic forces a non-PLCC part then dropping the LCD interface might reduce it enough.
Since circumstances seem to conspire to force the use of surface-mounted parts, I'm resigned to implementing FPGA projects using bought-in development boards with ready mounted chips. BurchEd produce such boards with connection headers on 0.1" grid.
On the positive side, such development kits usually have generous capacity chips. For example the BurchEd boards have a Spartan 2 XC2S200 in a 208-pin package. This has 1176 logic cells and 140 I/O pins. The ZX81 LCD design compiled to use 92 of the 192 logic cells and 75 I/O pins of the XC2S15, so there should be plenty of space for other circuitry. There's enough I/O pins for two ZX81s if you drop the seven LCD signals from the second!
