DECODE.PLD

from HSYNC pld	hsync	-->	_1	----------	24	--	VCC
from CPU	a13	-->	2		23	-->	!addressenable	to SHIFT pld
from CPU	a14	-->	3		22	-->	_a0	to EPROM/RAM address line
from CPU	a15	-->	4		21	-->	_a1	to EPROM/RAM address line
from CPU	!halt	-->	5		20	-->	_a2	to EPROM/RAM address line
from CPU	!m1	-->	6		19	-->	!romselect	to EPROM CE and OE
from CPU	_d6	-->	7		18	-->	!ramselect	to RAM CE and OE
from CPU	!rd	-->	8		17	-->	!nop	to SHIFT pld and NOP pld
from CPU	!rfsh	-->	9		16	-->	!wait	to CPU
from CPU	!mreq	-->	10		15	--	spare
from HSYNC pld	!vsync	-->	11		14	<--	!nmienable	from HSYNC pld
	GND	--	12		13	<--	!nmi	from HSYNC pld

The memory map decoder. Also, during character font data fetch cycles, pins 20-21 drive the LS bits of the memory bus to select one of the eight rows within a character cell.

Comments in green below were added by me

                PARTNO    decode;
                NAME      decode;
                DATE      12/11/98;
                REV       01 ;
                DESIGNER  isb ;

device g22v10;

pin 1 = hsync;   /* from HSYNC pld */
pin 2 = a13;     /* from CPU */
pin 3 = a14;     /* from CPU */
pin 4 = a15;     /* from CPU */
pin 5 = !halt;   /* from CPU */
pin 6 = !m1;     /* from CPU */
pin 7 = _d6;     /* from SHIFT pld */
pin 8 = !rd;     /* from CPU */
pin 9 = !rfsh;   /* from CPU */
pin 10 = !mreq;  /* from CPU */
pin 11 = !vsync; /* from HSYNC pld */

pin 23 = !addressenable;  /* to SHIFT pld */
pin 22 = _a0;             /* to EPROM/RAM address line */
pin 21 = _a1;             /* to EPROM/RAM address line */
pin 20 = _a2;             /* to EPROM/RAM address line */
pin 19 = !romselect;      /* to EPROM CE and OE */ 
pin 18 = !ramselect;      /* to RAM CE and OE */ 
pin 17 = !nop;            /* to SHIFT pld and NOP pld */ 
pin 16 = !wait;           /* to CPU */
/*pin 15 = spare;*/
pin 14 = !nmienable;      /* from HSYNC pld */
pin 13 = !nmi;            /* from HSYNC pld */

/* the character cell row counter output is enabled 
when the refresh signal is asserted 
and addressenable indicates the system is in character display mode
*/

_a0.oe = rfsh & addressenable;
_a1.oe = rfsh & addressenable;
_a2.oe = rfsh & addressenable;

/* the character cell row counter output is Asynchronously Reset
when the vertical sync signal is asserted.
This ensures it is starts from zero at the top of each video frame.
*/

_a0.ar = vsync;
_a1.ar = vsync;
_a2.ar = vsync;

/* the character cell row counter output is Synchronously Preset
when the non-maskable interrupt signal is asserted.
This .
*/

_a0.sp = nmienable;
_a1.sp = nmienable;
_a2.sp = nmienable;

/* The counter implementation.
A0 simply toggles on each clock cycle.
*/

_a0.d = !_a0;
_a1.d = _a1 $ _a0;
_a2.d = (_a2 $ (_a0 & _a1));

/* The expressions below compress the logic expressions.
They are not signals but more like #defines in C,
which are substituted into the logic equations above.
*/

romselect = (rfsh # mreq) & !a13 & !a14 & !a15; /*  0-8k */
ramselect = (rfsh # mreq) &  a13 & !a14         /*  8-16k & 40-48k */
          # (rfsh # mreq) &  a14                /* 16-32k & 48-64k */
          # (rfsh # mreq) & !a13 & !a14 &  a15; /* 32-40k */

addressenable = !a14 & !a15;  /* only char bitmaps in first 16k */
                              /* so true hires works above 16k  */

nop = !halt & m1 & !_d6 & a14 & a15;            /* force NOPs in 48-64k */

wait = !halt & nmi;