NOP.PLD

from CPU	!rd	-->	_1	----------	24	--	VCC
	!nop	-->	2		23	->-	!kbd	to KEYFIX pld
from keyboard or KEYFIX pld	id0	-->	3		22	--X	outputenable	not connected
from keyboard or KEYFIX pld	id1	-->	4		21	-->	d4	to CPU
from keyboard or KEYFIX pld	id2	-->	5		20	-->	d3	to CPU
from keyboard or KEYFIX pld	id3	-->	6		19	-->	d5	to CPU
from keyboard or KEYFIX pld	id4	-->	7		18	-->	d6	to CPU
not connected	id5	-->	8		17	-->	d2	to CPU
from SW6	id6	-->	9		16	-->	d7	to CPU
from cassette input circuit	id7	-->	10		15	-->	d0	to CPU
from CPU	!iorq	-->	11		14	-->	d1	to CPU
	GND	--	12		13	<--	a0	from CPU

This has two functions. It forces NOP codes on the data bus during video access cycles, and buffers inputs from the keyboard and tape input.

Comments in green below were added by me

                PARTNO    nop;
                NAME      nop;
                DATE      12/11/98;
                REV       01 ;
                DESIGNER  isb ;

device g22v10;

pin 1 = !rd;    /* from CPU */
pin 2 = !nop;   /* from CPU */
pin 3 = id0;    /* from keyboard or KEYFIX pld */
pin 4 = id1;    /* from keyboard or KEYFIX pld */
pin 5 = id2;    /* from keyboard or KEYFIX pld */
pin 6 = id3;    /* from keyboard or KEYFIX pld */
pin 7 = id4;    /* from keyboard or KEYFIX pld */
pin 8 = id5;    /* not connected */
pin 9 = id6;    /* from SW6 */
pin 10 = id7;   /* from cassette input circuit */
pin 11 = !iorq; /* from CPU */

pin 23 = !kbd;         /* to KEYFIX pld */
pin 22 = outputenable; /* not connected */
pin 21 = d4;	       /* to CPU */
pin 20 = d3;	       /* to CPU */
pin 19 = d5;	       /* to CPU */
pin 18 = d6;	       /* to CPU */
pin 17 = d2;	       /* to CPU */
pin 16 = d7;	       /* to CPU */
pin 15 = d0;	       /* to CPU */
pin 14 = d1;	       /* to CPU */
pin 13 = a0;	       /* from CPU */

// The keyboard is read at the standard ZX81 address, 
// i.e. when doing an I/O read with A0 low.

kbd = iorq & rd & !a0;

// The data bus is driven if the keyboard is being read
// or the NOP signal is asserted (during video)

outputenable = kbd # nop;

d0.oe=outputenable;
d1.oe=outputenable;
d2.oe=outputenable;
d3.oe=outputenable;
d4.oe=outputenable;
d5.oe=outputenable;
d6.oe=outputenable;
d7.oe=outputenable;

// This is a good way to conserve pins.
// If not a nop cycle, the data is simply the input pins,
// If it is a nop cycle, the data is zero.

d0 = !nop & id0;
d1 = !nop & id1;
d2 = !nop & id2;
d3 = !nop & id3;
d4 = !nop & id4;
d5 = !nop & id5;
d6 = !nop & id6;
d7 = !nop & id7;