SHIFT.PLD

The shift register for video generation.
The _d* inputs are from 1k resistors connected to CPU data lines. This chip takes the character data from these data lines and latches them internally. The character latch data later drives the ROM address lines when the ROM is required as a character font ROM.

Comments in green below were added by me

                PARTNO    shift;
                NAME      shift;
                DATE      12/11/98;
                REV       01 ;
                DESIGNER  isb ;

device v750;

pin 1 = _d1;    /* from 1k resistor connected to CPU data line */
pin 2 = _d0;    /* from 1k resistor connected to CPU data line */
pin 3 = _d7;    /* from 1k resistor connected to CPU data line */
pin 4 = _d2;    /* from 1k resistor connected to CPU data line */
pin 5 = _d6;    /* from 1k resistor connected to CPU data line */
pin 6 = _d5;    /* from 1k resistor connected to CPU data line */
pin 7 = _d3;    /* from 1k resistor connected to CPU data line */
pin 8 = _d4;    /* from 1k resistor connected to CPU data line */
pin 9 = clk6;   /* from HSYNC pld */
pin 10 = !rd;   /* from CPU */
pin 11 = !rfsh; /* from CPU */

pin 23 = _a3;            /* to EPROM/RAM address line */  
pin 22 = _a4;            /* to EPROM/RAM address line */
pin 21 = _a5;            /* to EPROM/RAM address line */
pin 20 = _a6;            /* to EPROM/RAM address line */
pin 19 = _a7;            /* to EPROM/RAM address line */
pin 18 = _a8;            /* to EPROM/RAM address line */
pin 17 = s0;	         /* video data out to video circuit */
pin 16 = !nop;           /* from decode PLD */
pin 15 = !blankedinvert; /* from HSYNC pld */
pin 14 = !addressenable; /* from DECODE pld */
pin 13 = !mreq;          /* from CPU */

// The ATV750 chips are like two 22V10 chips in a single package.
// There are not enough pins to connect them to the outside world,
// so the extra internal pins are called pinnodes.
// In this design, they are mainly used as a buried (i.e. internal) latch.

pinnode 34 = delayedrfsh;
pinnode 33 = q1;
pinnode 32 = q3;
pinnode 31 = q5;
pinnode 30 = q7;
pinnode 29 = q6;
pinnode 28 = q4;
pinnode 27 = q2;
pinnode 26 = q0;
pinnode 25 = charinvert;

pinnode 37 = latchednop;  /* shared with pin 16 */

// The video data latch Output Enable is asserted 
// when addressenable and Refresh are asserted

_a3.oe=rfsh & addressenable;
_a4.oe=rfsh & addressenable;
_a5.oe=rfsh & addressenable;
_a6.oe=rfsh & addressenable;
_a7.oe=rfsh & addressenable;
_a8.oe=rfsh & addressenable;

// The video data latch is clocked by the Read signal

_a3.ck=!rd;
_a4.ck=!rd;
_a5.ck=!rd;
_a6.ck=!rd;
_a7.ck=!rd;
_a8.ck=!rd;

// The video data latch inputs are from the memory data bus.
// NB from the memory side of the resistors, because the
// CPU side will be held to zero during video access.

_a3.d = _d0;
_a4.d = _d1;
_a5.d = _d2;
_a6.d = _d3;
_a7.d = _d4;
_a8.d = _d5;

// Character inversion is controlled by latched D7 

charinvert.ck=!rd;
charinvert.d = _d7;

latchednop.ck=!rd;
latchednop.d=nop;

delayedrfsh.ck=clk6;
delayedrfsh.d=rfsh & mreq & latchednop;
latch=!mreq & delayedrfsh;

// The ouput pins are clocked by the 6.5MHz clock signal. 

q0.ck=clk6;
q1.ck=clk6;
q2.ck=clk6;
q3.ck=clk6;
q4.ck=clk6;
q5.ck=clk6;
q6.ck=clk6;
q7.ck=clk6;

// The video data output latch data:

q0.d =			  latch & (_d0 $ charinvert);
q1.d = !latch & q0	# latch & (_d1 $ charinvert);
q2.d = !latch & q1	# latch & (_d2 $ charinvert);
q3.d = !latch & q2	# latch & (_d3 $ charinvert);
q4.d = !latch & q3	# latch & (_d4 $ charinvert);
q5.d = !latch & q4	# latch & (_d5 $ charinvert);
q6.d = !latch & q5	# latch & (_d6 $ charinvert);
q7.d = !latch & q6	# latch & (_d7 $ charinvert);

s0 = q7 $ blankedinvert;