Logic Debugging

In theory, you should be able to get logic designs by logical thought alone. In practice it is far quicker to solve problems if you can see what your logic is actually doing, as opposed to what you think it should be doing.

I managed to get a lot of my FPGA computer project working without much equipment, because the video display showed me a lot about what was working or not. However, when developing the serial-loading audio DAC logic I could not see or hear anything. An oscilloscope would have shown whether my project was producing the right number of clock pulses. A two-channel scope would have shown the relative timing of the clock and data signals. Storage scopes would hold waveforms for inspection.

So I shopped around for oscilloscopes. These are generally heavy and expensive. Traditional scopes have a long CRT with a small screen and a high voltage supply. Newer scopes often have flat LCDs instead, but are more expensive.

More recent scopes use a PC for display, and are therefore very small and light. But still not cheap, and only two channel.

Most of my work is digital so I didn't need to know the shape of waveforms. Logic analysers can view many channels of digital logic but historically have been very expensive.

The ANT Logic Analysers

These seemed to fit my needs and my thrifty budget. The 8-channel version (ANT8) has a 9-pin D-type connector, which connects to a cable with individual test clips. The 16-channel version (ANT16, £195) has a 20-pin header which easily mates with a 20-way ribbon-cable. In both versions, matching cables with test clips have to be bought seperately, costing over 10% of the logic analyser itself (£25 for the ANT16 connector).

Connecting and disconnecting lots of test clips is a fiddly chore, prone to errors and inadvertent short circuits. It is much better to be able to connect an analyser to target signals by a simple ribbon cable and IDC sockets.

The BurchEd FPGA headers were designed to match Hewlett-Packard logic analyser probe heads for easy connection. The current ANT16 pinout is similar but not exactly compatible.

Connecting the ANT16 to BurchEd FPGA boards

The figure below shows the pinout of the ANT16 and the data bus pinout of a BurchEd RAM board. Other BurchEd headers generally start assigning signals at pin 19 then proceed toward pin 1.

ANT16 header pin numbering BurchEd RAM board Data Bus header
as per the manual: as per the connector
(arrowhead at pin 1):
pin numbering consistent with
HP logic analyser probe heads:
trig out 20 19 trig in / clk in
ch15 18 17 ch14
ch13 16 15 ch12
ch11 14 13 ch10
ch9 12 11 ch8
GND 10 9 ch7
ch6 8 7 ch5
ch4 6 5 ch3
ch2 4 3 ch1
ch0 2 1 GND
trig out 1 2 trig in / clk in
ch15 3 4 ch14
ch13 5 6 ch12
ch11 7 8 ch10
ch9 9 10 ch8
GND 11 12 ch7
ch6 13 14 ch5
ch4 15 16 ch3
ch2 17 18 ch1
ch0 19 20 GND
PWR --- 1 2 --> !WEH
!WEL <-- 3 4 <-> D15
D14 <-> 5 6 <-> D13
D12 <-> 7 8 <-> D11
D10 <-> 9 10 <-> D9
D8 <-> 11 12 <-> D7
D6 <-> 13 14 <-> D5
D4 <-> 15 16 <-> D3
D2 <-> 17 18 <-> D1
D0 <-> 19 20 --- GND

The manual contradicts the connector marking, which caused my first attempt at making an adapter cable to fail. This is a mistake in the manual, because connectors have the convention of indicating pin 1 with an arrow. I told the manufacturers about this a long time ago, but they have not altered the manual to match the connector or vice versa. Nor added a note about this discrepancy.

I've chosen to believe the connector marking. That way, pins 12 to 20 are identical to those of the BurchEd/HP headers. The ANT16 has an extra ground pin on ribbon cable wire 11; if this is isolated then the wires for channels 8 to 15 can simply be shifted along one place. The trigger signals do not correspond well, so these are left seperate for connection to the system clock.

ANT16 adapter cable connections

This is the adapter I used successfully. It needs some assembly work, but not much more than a simple 1 to 1 cable. And far less than soldering 16 individual sprung probes. It will also avoid a lot of time and fiddling attaching such probes as well. Strain reliefs are recommended, as it may well be plugged/unplugged many times.

ANT16   wire   HP/Burched
 
GND   --- 20 --- 20 GND
ch0   --- 19 --- 19 D0
ch1   --- 18 --- 18 D1
ch2   --- 17 --- 17 D2
ch3   --- 16 --- 16 D3
ch4   --- 15 --- 15 D4
ch5   --- 14 --- 14 D5
ch6   --- 13 --- 13 D6
ch7   --- 12 --- 12 D7
GND   --- 11 NC    
ch8   --- 10 --- 11 D8
ch9   --- 9 --- 10 D9
ch10   --- 8 --- 9 D10
ch11   --- 7 --- 8 D11
ch12   --- 6 --- 7 D12
ch13   --- 5 --- 6 D13
ch14   --- 4 --- 5 D14
ch15   --- 3 --- 4 D15
trig in / clk in   --- 2 NC 3 !WEL
trig out   --- 1 NC 2 !WEH
        NC 1 VCC

I have asked USB Instruments if they would consider modifying their product to match the Hewlett-Packard pinout, but haven't heard anything back on that suggestion.

Note that although the ANT16 specification states a sampling rate of up to 500 MHz (2 ns each!), this requires well-engineered connections to be practical. Ideally 'MICTOR' connectors. Logic transitions in 2 ns have a huge slew rate and therefore much scope for crosstalk. Interleaved ground wires become necessary, and standard 50-thou pitch ribbon cable does not have these. You may have to rip a high-speed IDE cable in to two halves to get cable with interleaved wires. Alternatively you could use two 100-thou pitch ribbon cables, alternate wires grounded, and use one for the signals on each side of the header.

At modest speeds this should not be a problem.