Logic Device Architectures

The sketches below roughly illustrate the differences between the main logic device architectures.

Conventional Discrete Fixed Logic

PROM based Programmable Logic

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0 0 0			Logic
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
				¯	¯	¯	¯	¯	¯	¯	¯

Fixed 'AND' array rows decode every address.
Doubles in size for every input pin.

Programmable 'OR' array columns
define outputs for each address.

Pinout is fixed, but the user can rearrange the inputs (address lines) and outputs (data)

Signal routing can be changed by the logic equations.

Small 74LS family PROMs were once sometimes used for programmed logic, but were soon replaced by SPLDs.

Simple Programmable Logic Device (SPLD)

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'AND'								'OR'	L	«

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									L	«

									L	«

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									L	«

Programmable 'AND' array only decodes the
specific input pin combinations of interest.
The programmable 'OR' arrays are still present,
but limited to a few terms per logic cell.
This improves the device speed.
The sketch on the left shows a device with
just two 'OR' terms per logic cell,
to keep the diagram size reasonable.

Logic cells can also be clocked in some devices.

Signal routing can be changed by the logic equations.

Programming is relatively simple, about the same complexity level as assembler. Simple programs like CUPL turn a list of logical expressions into fuse-maps for the arrays in the specified device.

AMD were early exponents of SPLDs.
Lattice produce some that are in-site programmable.

The 22V10 is a very popular architecture for SPLDs,
having 22 I/O pins of which 10 can be used as outputs.

Complex Programmable Logic Device (CPLD)

		^ v	^ v	^ v	^ v	^ v	^ v	^ v	^ v
		L	L	L	L	L	L	L	L
«	L	Programmable routing resource								L	«
«	L									L	«
«	L									L	«
«	L									L	«
«	L									L	«
«	L									L	«
«	L									L	«
«	L									L	«
		L	L	L	L	L	L	L	L
		^ v	^ v	^ v	^ v	^ v	^ v	^ v	^ v

The key feature of this architecture is the arrangement of logic cells on the periphery of a central shared routing resource.

The device on the left is roughly equivalent of four of the devices above, connected together.

Now, programming is a little harder because the signal routing is not a trivial task. This is similar to the tasks required for routing signals in PCBs.
CPLDs are typically programmed in ABEL.
Using our programming language analogy, this has been compared to BASIC.

Altera were early exponents of CPLDs, producing many with EPROM-based technology. CPLDs are now also available using EEPROM or RAM technology, from Atmel or Xilinx fro example.

The 22V10 is a very popular architecture for SPLDs,
having 22 I/O pins of which 10 can be used as outputs.

Field Programmable Gate Array (FPGA)

^
v

<->

^
v

This architecture uses a 2-dimensional array of logic cells as islands in a sea of routing resources.

Routing is more complex than it is for CPLDs.
FPGAs are typically programmed in languages like Verilog or VHDL. These are high-level languages, because manual lower level design becomes impractical as designs become large.

Using our programming language analogy, Verilog has been compared with C and
VHDL with ADA. Both have strong and weak points, and both are popular.
VHDL is said to be strongly typed, and Verilog to be less so. Verilog allows things that VHDL might not, and allows more low-level design control. VHDL on the other hand allows greater high-level design control.

A rough look at the job adverts and projects in newsgroups seems to indicate VHDL is used more often, but skills learnt in Verilog are largely useable in VHDL.

Xilinx were the first big player in FPGAs, using RAM-based logic cells. Altera have since become a major player.

Programmable Logic Architectures

Conventional Discrete Fixed Logic

PROM based Programmable Logic

Simple Programmable Logic Device (SPLD)

Complex Programmable Logic Device (CPLD)

Field Programmable Gate Array (FPGA)