| !count | --> | 1 | --3242 - | 28 | --- | Vcc |
| ref_en | --> | 2 | 27 | <-- | r7 | |
| row_en | --> | 3 | 26 | <-- | c7 | |
| nc | --- | 4 | 25 | <-- | r5 | |
| r1 | --> | 5 | 24 | <-- | c5 | |
| c1 | --> | 6 | 23 | <-- | r4 | |
| r2 | --> | 7 | 22 | <-- | c4 | |
| c2 | --> | 8 | 21 | <-- | r3 | |
| r0 | --> | 9 | 20 | <-- | c3 | |
| c0 | --> | 10 | 19 | --> | !m6 | |
| !m0 | --> | 11 | 18 | --> | !m3 | |
| !m2 | --> | 12 | 17 | --> | !m4 | |
| !m1 | --> | 13 | 16 | --> | !m5 | |
| gnd | --- | 14 | 15 | <-- | !ce |
Chip usually shown with A0...13 where A0...6 is the row address and A7...13 is the column address.
It is only enough for 16K DRAM chips, though it has been used in bigger RAM packs with extra logic for the extra address bits.
Only useful for repairing old equipment these days, since you can get more than 16K static RAM in the same package size.
I've heard complaints about the timing, in that it is easy to get timing wrong with this chip.