6520 / 6821 PIA

Pinout

Vss --- 1 -6520 PIA-
-6821 PIA-		 40 <-- ca1
pa0 <-> 2 39 <-- ca2
pa1 <-> 3 38 --> !irqa
pa2 <-> 4 37 --> !irqb
pa3 <-> 5 36 <-> a1
pa4 <-> 6 35 <-> a0
pa5 <-> 7 34 <-- !rst
pa6 <-> 8 33 <-> d0
pa7 <-> 9 32 <-> d1
pb0 <-> 10 31 <-> d2
pb1 <-> 11 30 <-> d3
pb2 <-> 12 29 <-> d4
pb3 <-> 13 28 <-> d5
pb4 <-> 14 27 <-> d6
pb5 <-> 15 26 <-> d7
pb6 <-> 16 25 <-- ph2
pb7 <-> 17 24 <-- cs1
cb1 <-> 18 23 <-- !cs2
cb2 <-> 19 22 <-- cs0
Vcc --- 20 21 <-- r/!w

Software structure

PIA controls various I/O.
In the Atari 800XL: base address = $D300

struct PIA	=	// a standard 6520 chip
{
	byte	PORTA;	// Port A
	byte	PORTB;	// Port B
	byte	PACTL;	// Port A Control
	byte	PBCTL;	// Port B Control
};

Hardware structure

Approximate VHDL entity only!

entity PIA_6520is	-- a standard 6520 chip
port(
	n_rst:	in	std_logic;	-- Reset
	n_wr:	in	std_logic;	-- Read / Not Write
	ph2:	in	std_logic;	-- CPU clock phase 2
	cs0:	in	std_logic;
	cs1:	in	std_logic;
	n_cs2:	in	std_logic;
	a:	in	std_logic_vector(1downto 0);
	d:	inout	std_logic_vector(7downto 0);
	pa:	inout	std_logic_vector(7downto 0);	-- Port A
	ca:	inout	std_logic_vector(2downto 1);	-- Port CA
	pb:	inout	std_logic_vector(7downto 0);	-- Port B 
	cb:	inout	std_logic_vector(2downto 1);	-- Port CB
	n_irqa:	out	std_logic;	-- interrupt request A
	n_irqb:	out	std_logic;	-- interrupt request B
	);
end entity PIA_6520;