6522 / 65C22 VIA

Pinout

Software structure

struct VIA	=	// a standard 6522 chip
{
	byte	PORTB;	// Port B
	byte	PORTA;	// Port A
	byte	DDRA;	// Port B Control (Data Direction Register B)
	byte	DDRB;	// Port A Control (Data Direction Register A)
			// Write (R/W = L) | Read (R/W = H)
	byte	T1C_L;	// T1 Low-Order Latches | T1 Low-Order Counter
	byte	T1C_H;	// T1 High-Order Counter| T1 High-Order Counter
	byte	T1L_L;	// T1 Low-Order Latches
	byte	T1L_H;	// T1 High-Order Latches
	byte	T2C_L;	// T2 Low-Order Latches | T2 Low-Order Counter
	byte	T2C_H;	// T2 High-Order Counter
	byte	SR;	// Shift Register
	byte	ACR;	// Auxiliary Control Register
	byte	PCR;	// Peripheral Control Register
	byte	IFR;	// Interrupt Flag Register
	byte	IER;	// Interrupt Enable Register
	byte	PORTA_NH;	// Same as Register 1 except no handshake.

};

Hardware structure

Approximate VHDL entity only!

entity VIA_6522 is	-- 
port(
	n_rst:	in	std_logic;	-- Reset
	n_wr:	in	std_logic;	-- Read / Not Write
	ph2:	in	std_logic;	-- CPU clock phase 2
	cs1:	in	std_logic;
	n_cs2:	in	std_logic;
	rs:	in	std_logic_vector(3 downto 0);
	d:	inout	std_logic_vector(7 downto 0);
	pa:	inout	std_logic_vector(7 downto 0);	-- Port A
	ca:	inout	std_logic_vector(2 downto 1);	-- Port CA
	pb:	inout	std_logic_vector(7 downto 0);	-- Port B 
	cb:	inout	std_logic_vector(2 downto 1);	-- Port CB
	);
end entity VIA_6522;

Data Sheet

For full details see the R6522 Rockwell Versatile Interface Adapter (VIA) data sheet (Zipped TIF)

Pinout comparison: