68K CPU

Pinout

Hardware structure

Approximate VHDL entity only!

entity CPU_68K is	--
port(
	A:	out	std_logic_vector(23 downto 0);	-- Address bus
	D:	inout	std_logic_vector(15 downto 0);	-- Data bus
	n_AS:	out	std_logic;			-- Address Strobe
	n_UDS:	out	std_logic;			-- Upper Data Strobe
	n_LDS:	out	std_logic;			-- Lower Data Strobe
	R_n_W:	out	std_logic;			-- Read / Not Write
	n_DTACK: in	std_logic;			-- Not Data Transfer Acknowledge
	n_BG:	out	std_logic;			-- Not Bus Grant 
	n_BGACK: in	std_logic;			-- Not Bus Grant Acknowledge
	n_BR:	in	std_logic;			-- Not Bus Request
	CLK:	in	std_logic;			-- Clock
	n_HALT:	inout	std_logic;			-- Not Halt
	n_RESET: inout	std_logic;			-- Not Reset
	n_VMA:	out	std_logic;			-- Not Valid Memory Address
	E:	out	std_logic;			-- Enable
	n_VPA	in	std_logic;			-- Not Valid Peripheral Address
	n_BERR	in	std_logic;			-- Not Bus Error
	n_IPL	in	std_logic_vector(2 downto 0);	-- Not Interrupt Priority Level
	FC	out	std_logic_vector(2 downto 0);	-- Function Code
	);
end entity CPU_68K;

Register Set