| MPX | <-- | 1 | -HCS10017- | 40 | --> | MA6? |
| MA5? | <-- | 2 | 39 | --> | MA7? | |
| MA4? | <-- | 3 | 38 | --> | MA0? | |
| MA3? | <-- | 4 | 37 | --> | MA2? | |
| D5 | <-> | 5 | 36 | --> | MA1? | |
| GND | --- | 6 | 35 | |||
| CLK | --> | 7 | 34 | <-> | D6? | |
| D0 | <-> | 8 | 33 | <-- | A9? | |
| CAS | <-- | 9 | 32 | <-- | A8? | |
| RAS | <-- | 10 | 31 | <-- | A10? | |
| D2 | <-> | 11 | 30 | <-- | A15 | |
| D3 | <-> | 12 | 29 | <-- | A14 | |
| D4 | <-> | 13 | 28 | <-- | A13? | |
| PHI_OUT | <-- | 14 | 27 | <-- | R/!W | |
| 15 | 26 | --> | !MAP | |||
| SYNC | <-- | 16 | 25 | --> | !VIA1_CS | |
| D1 | <-> | 17 | 24 | Vcc | ||
| D7? | 18 | 23 | ||||
| BLUE | <-- | 19 | 22 | |||
| GREEN | <-- | 20 | 21 | --> | RED |
Pin directions not known for certain.
Approximate VHDL entity only!
entity HCS10017 is port( A: out std_logic_vector(15 downto 0); -- address RAS: out std_logic; -- MPX: out std_logic; -- CAS: out std_logic; -- SYNC: out std_logic; -- RED: out std_logic; -- GREEN out std_logic; -- BLUE: out std_logic; -- ) end entity HCS10017;