HD46505 (CRTC) CRT CONTROLLER

FEATURES

The HD46505 (CRTC) is a peripheral chip of HMCS6800 Microcomputer LSI families. It is designed in order to provide a simple and effective means of interfacing the raster scan CRT display to MPU bus. Its primary function is to generate the proper refresh address and video timings according to display format.

HD46505 is applicable to wide range of raster scan displays.

It is optimized for hardware/software balance in order to achieve integration of complex CRT interface functions and to maintain flexibility. Applications include intelligent CRT terminals, information display systems and video games.

PIN ARRANGEMENT

BLOCK DIAGRAM

HMCS 6800 SYSTEM BLOCK DIAGRAM

  A -->
D <->		 MPU (HN46800)
A -->
D <--		 ROM (HN46830A)
A -->
D <->		 RAM (HN46810A)
A -->
D <->		 PIA (HN46821)
A -->
D <->		 ACIA (HN46850)
A -->
D <->		 CRTC (HN46505) <-> CRT

CRTC (HD46505) BLOCK DIAGRAM

      Character
clock
V		    
Address
and
Control		 --> Select
and
Control		     --> Video
Control		 --> Video Control
--> Raster Address
    |
|
|
|
|
v		     V --> Refresh Memory Address
--> Address
generator
   
Data bus <-> Control
registers		 --> --> Light pen
control		 <-- Light pen

HD46505R (CRTC) is an exclusive LSI controller to interface the microcomputer HD46800D and CRT display of raster scan type.

HD46505R (CRTC) is one of HMC6800 LSI family and has a perfect compatibility about the data line and control line with MPU (HD46800D).

The main function of CRTC is to generate necessary timing signals for a CRT display of raster scan type according to the specification programmed by MPU. Therefore CRTC is applicable to very wide CRT displays such as a small size and low level character display, a large size and high level limited graphic display and raster type full graphic display by the designed feature, that is, programmable controller.

FUNCTIONS OF HD46505R (CRTC)

Item Function of HD46505R (CRTC) Remark
Function
of
CRTC		 Programmable
structure
of a picture		 Horizontal scanning interval Programmable by one character interval unit
Vertical scanning interval (Row unit) Programmable by one row interval unit.
Vertical scanning interval (Fine control) Programmable by one raster unit.
Displayed character number of one row  
Displayed character number of one picture
Raster number of one row Vertical dot number of one character + row space
Horizontal displayed position on CRT Possible by programming the output timing of synchronous signals.
Vertical displayed position on CRT
Pulse width of the horizontal synchronous signal  
Cursor Display Displayed position of cursor on a picture Internal cursor register of 14 bit.
Cursor format  
Cursor blink and its cycle Blink cycle is selectable one of 16 or 32 frame cycle.
Scan mode Non interlace mode Selectable one of these three modes.
Interlace sink mode
Interlace sink and video mode
Light Pen Internal light pen register of 14 bit  
Addressing of
refresh memory		 Put out the refresh memory address of 14 bit Accessable refresh memory of 16K words max.
Programmable
start address		 Internal start address register of 14 bit
(Able to determine the display start address
on the refresh memory by program.)		 Operations such as paging, scrolling etc. are usable.
LSI Structure
 Power supply Single +5V  
Bus function Directly connectable with HMCS6800
HMCS6800 family.		  
Process N channel Silicon gate E/D MOS
Operation Perfect static circuit
Package 40 pin Dual In Line type
CRTC Expandability Character display Alpha numeric character and other character
Limited (simple type) graphic display Graphic display (Raster scan type)
Full graphic display
Color display, Blink of displayed character  
Cluster control

FUNCTIONS OF SIGNAL LINE

Internal signals of HD46505R (CRTC) are composed of 13 interface signals with MPU and 25 interface signals with CRT display.

INTERFACE SIGNAL WITH MPU

Bi-directional Data Bus (D0...D7)

Bi-directional data bus (D0...D7) are used for the data transfer between CRTC and MPU. Data bus output is a three-state buffer and is in high impedance state except that MPU reads the data of CRTC.

READ/WRITE (R/!W)

Read/Write Signal (R/!W) controls the direction of data transfer between MPU and CRTC, that is, the data of CRTC is transferred to MPU while R/W is in "High" level and the data of MPU is transferred to CRTC while R/W is in "Low" level.

CHIP SELECT (!CS)

Chip select signal (!CS) is a signal to address CRTC chip and MPU can execute the operation of read/write to the internal registers of CRTC only when !CS is in "Low" level. Normally this signal is obtained by decoding the address signals of MPU under the condition that VMA signal of MPU is in "High" level.

REGISTER SELECT (RS)

Register select signal (RS) is used for separating internal registers into one address register and 18 control registers, that is, the address register is selected while RS is in "Low" level and control register are selected while RS is in "High" level.
Normally the LSB of MPU's address bus (A0) is used for this signal.

ENABLE (E)

Enable signal (E) is used for a strobe signal when MPU read or writes internal registers of CRTC. Normally PH2 clock of MPU is used for this signal.

Reset (!RES)

Reset signal (!RES) is an input signal to reset CRTC externally. Internal states of CRTC become as follows when !RES becomes "Low" level.

  1. Internal counters of CRTC are all cleared and stopped their operations.
  2. All output signals of CRTC become "Low" level.
  3. Internal address register and control registers of CRTC keep former states regardless of RES.

This signal has different functions from that of HMCS6800 family LSls and its remarks are as follows.

  1. !RES signal is usable as reset signal only when LPSTB signal is in "Low" level.
  2. Output signals of MA0...MA13, RA0...RA4, become "Low" level synchronizing with the "Low" level of CLK signal after !RES becomes a "Low" level. (CLK signal is necessary at least one cycle in order to make those output signals "Low" level.)
  3. CRTC starts display operation immediately after !RES becomes from "Low" level to "High" level and reset is canceled.

INTERFACE SIGNAL WITH CRT DISPLAY EQUIPMENT

CHARACTER CLOCK (CLK)

Character clock signal (CLK) is used for a standard clock of CRTC's internal operation. This signal is given by the external high-speed dot timing logic.

HORIZONTAL SYNCHRONIZATION (HSYNC)

Horizontal synchronization signal (HSYNC) is used as a driving signal of horizontal deflection circuit of CRT display equipment.
Pulse width of vertical synchronization signal is fixed to 16 rasters cycle.

DISPLAY TIMING (DISPTMG)

This signal is a signal that shows picture display interval of horizontal and vertical deflection. Video signal has to be sent to CRT display equipment only while this signal is in "High" level.

REFRESH MEMORY ADDRESS (MA0...MA13)

Refresh memory address (MA0...MA13) is used for memory address to refresh the displayed picture on CRT display equipment at a constant cycle. Address of 16K words (0...16383) max. can be designated by this address signal. Therefore paging to 8 pages is possible, for instance, in case of the display equipment of 2000 characters.

RASTER ADDRESS (RA0...RA3)

Raster address (RA0...RA3) is used for a raster select signal of character generator and pattern generator.

CURSOR DISPLAY (CUDISP)

Cursor display signal (CUDISP) is a video signal to display the cursor on CRT display equipment. This signal is inhibited while DISPTMG is in "Low" level. Normally this signal is mixed with character video signal and sent to CRT display equipment.

LIGHT PEN STROBE (LPSTB)

Light pen strobe signal (LPSTB) is the detected pulse of character from the light pen. The content of refresh memory address (MA0...MA13) shown in Fig. 5 is set in the light pen register of 14 bit when this signal is put in. Memory address being set should be compensated by software for a delay time between display equipment and light pen and its control circuit.

Internal Registers of HD46505R (CRTC)

!CS RS Addr. Reg.
no.		 Register
name		 Program
Unit		 Read Write Data Bit Notes
43210
1 x xxxxx x Invalid - - -                 -
0 0 xxxxx AR Address Req.   x                
0 1 00000 R0 Horizontal total character number Character x 0                 1,7
00001 R1 Horizontal displayed character number ditto                  
00010 R2 Positionof horizontal sync. pulse ditto                  
00011 R3 Pulse width of horizontal sync. pulse ditto            
00100 R4 Vertical total Line character number                   7
00101 R5 Total raster adjust Raster              
00110 R6 Vertical displayed character number Line                 2
00111 R7 Position of vertical sync. pulse ditto                 7
01000 R8 Interlaced mode --   V S 3
01001 R9 Maximum raster Raster             4,7
01010 R10 Cursor start raster ditto   B P           5,6
01011 R11 Cursor end ditto             6
01100 R12 Start address (H "                
01101 R13 Start address (L) -                  
01110 R14 Cursor(H) - 0                
01111 R15 Cursor(L) - 0                  
10000 R16 Light Pen(H) - 0 x                
11111 R17 Light Pen (L) - 0 x                  

Notes:

  1. Set data should be odd in case of interlaced mode (R8 = 1 or 3).
  2. Set data should be N/2 (N is a real displayed row number) when R8 = 3.
  3. V designates video mode when S = 1. S designates interlaced mode.
  4. Set data should be odd in case of R8 = 3.
  5. B designates cursor blink and P designates blink cycle.
    ON 16 or 32 fields interval
    OFF
    ON
    OFF
    ON
  6. Combination of start raster and end raster should be (odd-odd) or (even-even) when R8 =3.
  7. (Set data) = (Designated data) - 1.
    *
    0 "Low" level,
    1 "High" level

INTERLACE MODE

V S Mode
x 0 Non interlace mode
0 1 Interlace sync mode
1 Interlace sync and video mode

CURSOR DISPLAY

B P Cursor Display Mode
0 0 Cursor doesn't blink.
1 Cursor isn't displayed.
1 0 Cursor blinks by the cycle of 16 fields interval.
1 Cursor blinks by the cycle of 32 fields interval.

RESTRICTIONS ON PROGRAMMING OF HD46505R (CRTC)

  1. 0 < Nhd < Nht+1 <= 256
  2. Nht: Odd number (When interlace sink or interlace sync and video mode)
  3. 0 < Nvd < Nvt <= 128
  4. Nhsp + Nhsw < Nht + 1
  5. Nvsp <= Nvt
  6. 0 <= Ncstart <= Ncend <= Nr
  7. One of next two cases should be selected in case of interface sync and video mode
    1. Ncstart, Ncend are both even.
    2. Ncstart, Ncend are both odd.

Meanings of symbols mentioned above.

Set data of Register: Nht (Horizontal total character number)-1
Nhd Horizontal displayed character number
Nvt (Vertical total character number)-1
Nvd Vertical displayed character number
Nhsp (Position of horizontal sync.)-1
Nvsp (Position of vertical sync.)-1
Nr Maximum raster address
Ncstart Cursor start raster address
Ncend Cursor end raster address

MAXIMUM RATINGS

Item Symbol Value Unit NOTE
Supply Voltage* Vcc -0.3 to 7.0 V Permanent device damage may occur if
ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS.

Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Input Voltage* Vin -0.3 to 7.0 V
Operating Temperature Topr -20 to 75 ºC
Storage Temperature Tsig -55 to 150 ºC

* In respect to Vss (GND)

RECOMMENDED OPERATING CONDITIONS

Item Symbol Value Unit NOTE
Min. Typ. Max.
Supply Voltage* Vcc 4.75 5.0 5.25 V Permanent device damage may occur if
ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to
RECOMMENDED OPERATING CONDITIONS.

Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Input Voltage* VIL
VIH		 -0.3
2.0		 -- 0.8
Vcc		 V
Operating Temperature Topr -20 25 75 ºC
Storage Temperature Tsig -55   150 ºC

* In respect to Vss (GND)

ELECTRICAL CHARACTERISTICS (Vcc = 5V ± 5%, Vss = 0V, Ta = -20º to +75ºC)

Item Symbol Test Condition min. typ.* max. Unit
Input "High" Level Voltage All Inputs VIH   2.0 -- Vcc V
Input "Low" Level Voltage All Inputs VIL   -0.3 -- - 0.8 V
Input Leak Current Inputs without D0...D7 IIN VIN = 0 to 5.25V 1.0 -- 2.5 pA
Input Current at TriState (OFF) D0...D7 ITSI VIN = 0.4 to 2.4V 2.0 -- 10 pA
Output "High" Level Voltage D0...D7 VOH ILOAD = -205 pA 2.4 -- -- V
Other outputs ILOAD = -100 pA
Output "Low" Level Voltage All Outputs VOL ILOAD = 1.6 mA     0.4 V
Input Capacitance D0...D7 CIN VIN = 0V,
Ta = 25ºC
f = 1MHz		 -- -- 12.5 pF
Other Inputs -- -- 10
Output Capacitance D0...D7 COUT -- -- 10.0 pF
Power Dissipation   PD   -- 600 1000 mW

* Value at Ta = 25ºC, VCC = 5V.

TIMING CHARACTERISTICS

Control Signal Timing of CRTC

Item Symbol Test Condition min. typ.* max. Unit
Clock Frequency FC Fig. 4 -- -- 3.0 MHz
Clock Pulse Width "Low" Level PWCL 150 -- -- ns
"High" Level PWCH 150 -- -- ns
Rise/Fall Time of Clock Input tcr, tcf -- -- 15 ns
Memory-Address Delay Time tMAD   -- 160 ns
Raster-Address Delay Time tRAD -- -- 160 ns
Display-Timing Delay Time tDTD -- -- 250 ns
H. Sync. Delay Time tHSD -- -- 250 ns
V. Sync. Delay Time tVSD -- -- 250 ns
Cursor Display Delay Time tCDD -- -- 250 ns
Pulse Width of Light Pen Strobe PWLPH 80 -- -- ns
Uncertain time of light pen strobe reception. tLPD1, tLPD2 Fig. 5 -- -- 10 ns

BUS TIMING CHARACTERISTICS

READ SEQUENCE

Item Symbol Test Condition min. typ.* max. Unit
Enable Cycle Time tCYCE Fig. 2 -- -- 1000 ns
Enable Pulse Width "High" Level PWEH 450 -- -- ns
"Low" Level PWEL 400 -- -- ns
Setup Time of ADDRESS-ENABLE tcr, tcf 140 -- -- ns
Data Delay Time tDDR -- -- 320 ns
Data Hold Time tH 10 -- -- ns
Rise/Fall Time of Enable Input tEr,tEf -- -- 25 ns
Address Hold Time tAH 10 -- -- ns
Data Access Time tacc -- -- 460 ns

FIGURE 2. READ SEQUENCE

WRITE SEQUENCE

Item Symbol Test Condition min. typ.* max. Unit
Enable Cycle Time tCYCE Fig. 3 -- -- 1000 ns
Enable Pulse Width "High" Level PWEH 450 -- -- ns
"Low" Level PWEL 400 -- -- ns
Setup Time of ADDRESS-ENABLE tcr, tcf 140 -- -- ns
Data Setup Time tDSW 195 -- -- ns
Data Hold Time tH 10 -- -- ns
Rise/Fall Time of Enable Input tEr,tEf 25 -- -- ns
Address Hold Time tAH 10 -- -- ns
Data Access Time tacc -- -- 460 ns

FIGURE 3. WRITE SEQUENCE

FIGURE 4. CRTC TIME CHART

This figure shows the timing relationship of CLK signal and output signals.

FIGURE 5. INPUT TIMING OF LPSTB AND SET MEMORY ADDRESS

Refresh memory address M+2 is set in the Light Pen Register when the rise of LPSTB is put in during this interval.

FIGURE 6. LOAD CIRCUIT

C = 130pF (D0...7)
30 pF (Other outputs)
R = 11 K (D0...7)
24K (Other outputs)
D1..D4 1S2074

FIGURE 7. CHARACTER DISPLAY SYSTEM EXAMPLE USING HD46505R (CRTC)