Common to any CRT control circuit is the requirement that the Video Display RAM used to store the currently displayed text be accessible by both the system MPU to chanqe the display and the CRT display logic to keep the screen active. This is illustrated by the diagram in Figure 1, which shows the dual access nature of the Video Display RAM. The SY6545 CRT Controller permits several methods of memory sharing to be implemented:
MPU Priority
With this technique, any MPU request immediately has access to the Video Display RAM, over riding any current access being made by the CRT logic. PH1/PH2 Interleave This method "time-shares" the memory. Each MPU clock cycle is split so that both the MPU and the CRT logic have immediate access.
Transparent Addressing - Blanking
This technique permits MPU access to the Video Display RAM to occur only during non-display times both vertical and horizontal.
Transparent Addressing - PH1/PH2 Interleave
In this method, the MPU accesses the RAM through the CRT Controller with PH1/PH2 "time-sharing".
Each of these methods requires different circuit implementations and variations in how the MPU programs are constructed.