Figure 2 is a detailed schematic of the CRT control logic for this scheme and Figure 3 shows the associated timings. Several points are noteworthy:
In Figure 2, the 74157 multiplex switches are used to select either the CRTC or the MPU as the addressing inputs to the Video Display RAM. Whenever the MPU address bus selects a Video Display RAM address, the multiplex switches immediately gate the MPU address to the RAM, de-selecting the CRTC addresses. Table 1 summarizes the address decoding for Figure 2.
The 74243 bus transceivers are selected in conjunction with the multiplex switches to connect the MPU data bus to the Video Display RAM whenever it is selected by the MPU. The direction of the data through the transceivers is determined by the level of the R/!W line on the MPU. Further, they are active only during PH2 time of the MPU cycle, since data transfers in the MPU are only done at that time. The controls for the transceivers GBA and !GAB are determined by Table 2.
In Figure 3, note that the dot time is 80 nsec and the character time is 640 nsec (8 dots/character). The address propagation delays (6545) and the RAM (2114) and ROM (2316B) access times determine when the dot pattern data is available to be loaded into the shift register. The load strobe may occur any time when the dot pattern is valid. In this example, the load strobe is generated early in the character clock cycle, approximately coincident with the leading edge of the time when a delayed Cursor signal would be available. In this way, video data from the shift register may be modified, highlighted, reversed, etc by the Cursor signal, directly. Note that since the load strobe for a character occurs in the CCLK cycle following when the address was generated, it is necessary to program the Cursor to be delayed one cycle, a programmed function in the SY6545. For the same reason, Display Enable must be delayed one cycle, as well.
The effect of MPU updates to the Video Display RAM may be understood with Figures 2 and 3. The only way any MPU operation can disturb the video appearance is if the MPU write or read occurs simultaneously with the shift register load signal. If this happens the shift register will be loaded with wrong data and some spurious flashing will be visible on the screen. Updates. during blanking times have no visible effects.
