Figure 4 is a detailed schematic and Figure 5 illustrates the timing for this method.
In Figure 4, note that the 74157 multiplex switches are controlled by the MPU clock PH0 (IN). Further, PH0 (IN) is nothing more than the CCLK, so that the system MPU and the CRTC are exactly synchronized. In this way, the address inputs to the Video Display RAM repetitively switch between the MPU address lines and the CRTC address outputs. Thus, MPU operations may be done directly, since the MPU address is always on the Video Display RAM during PH2 time (time when PH0 is high). As a result, MPU program operations on the RAM are identical for this mode as for the MPU Priority scheme; only the hardware is different. The address decoding is repeated in Table 3 for clarity.
The 74243 bus transceivers are decoded identically, as well:
In Figure 5, the same dot and character rates are used but the MPU clock rate is no longer independent. Instead, the MPU PH0 (IN) is controlled directly from the character clock. In this [text missing from original document] nsec .
Note that the CRTC propagation delays (MA and RA outputs and the MPU propagation delays (A0 - A15), both occur during times when they are not selected by the multiplex switches. Thus, the RAM address inputs are clean and are only affected by the switching time of the 74157 units (typically 10-15 nsec).
An additional 8-bit latch (the 74373 in Figure 4) is needed to hold the ASCII character from the Video Display RAM until the ROM output is loaded into the Shift Register. This is required because the cumulative access times are too slow to respond to the rapidly changing addresses. Alternative to the latch, faster memories RAM and ROM could be used, but this is strictly an economic issue.
Because MPU operations take place during time intervals where the CRTC is not utilizing the memory, updates cause no visible screen effects.
