Transparent Addressing is a unique method in the SY6545 which permits memory updates changes in Video Display RAM to occur during horizontal and vertical blanking re-trace times, thus, no visible screen perturbations result. Figure 6 shows the detailed circuit schematic and Figure 7, the related timings.
Note the absence: of the 74157 multiplex switches in Figure 6. Multiplexing is done internal to the SY6545 in this mode. When memory updates are required, the SY6545 generates the required memory address on the MA output lines and a strobe on RA4. This causes the required update to occur.
The data bus interface for the MPU is implemented with bi-directional latches, in this case two 74373 latch units. Bi-directional operation permits both writes and reads to be done by the MPU.
The RAM is not addressed as a memory block, as in the previous cases, but only the latch need be selected. In effect, then, the memory appears as a port to the MPU. Table 5 summarizes this.
Notice the special nature of the addressing:
When addresses 4000 or 4001 are generated by the MPU, only the respective CRTC function is selected; the latches are unaffected.
When address 4003 is generated to select the latches, however, the CRTC DATA function is simultaneously selected. This is required for correct transparent Addressing operation.
The RA4 pin of the SY6545 functions as a special strobe for transparent addressing. Since memory accesses onlv occur during screen blanking times (horizontal or vertical, some signal must be used to trigger these operations. RA4 does this on the SY6545.
The operation of the control logic is crucial to understanding this particular implementation. Figure 8 illustrates the logic and Figure 9, timing details for the control of memory operations.
The timings in Figure 8 are for the case of successive MPU writes into the RAM. The operation is initiated when the MPU selects REG 31 in the SY6545. This has no effect on the control logic, but causes the CRTC SY6545 to begin its transparent update sequence.
When the display timing enters a blanking interval horizontal or vertical, the CRTC puts the internal Update Address (UA) on the MA lines and generates a strobe on RA4. Since the WRITE PENDING line is low, no memory write occurs but, instead a read is activated and the memory data is stored in the lower of the two latches. This step is required, since the CRTC does not yet know whether a memory write or a read is to be done. Hence, it assumes a read and fetches the data in advance.
Next in the sequence, the MPU either writes data into or reads from the latch. In Figure 9, write cycles are assumed, since this is the more complex example. Writ-ing into the latches sets the cross-coupled latch and the WRITE PENDING signal becomes high. This operation also causes a select on the CRTC, so it knows the data has been stored in the latch. At the next available blank time (may be immediate) the UA is again put on the MA lines and another RA4 strobe is generated. Since the WRITE PENDING line is high, this causes the latch !OUT and the memory !WE to simultaneously go low, in turn generating the appropriate memory write operation. At the next negative edge of the CCLK, WRITE PENDING returns low, causing !OUT and !WE to terminate. Internal to the CRTC, the UA is incremented to UA + 1 and another update is generated. As before, since WRITE PENDING is low, an automatic memory read occurs ir anticipation of the next MPU operation, which may be a write or a read.
The sequence may continue indefinitely and will end up with an automatic read cycle after the last MPU write has been done. The CRTC may then be de-selected by programming its internal register select to some register other than REG 31, which is only used for transparent addressing.
In the case wherein the MPU is to read successive locations, the timing of Figure 9 changes slightly. WRITE PENDING never goes high, so no memory write cycles are generated. Instead, only a series of automatic reads occurs. Figure 10 illustrates this.
Note that Figure 7. the routine timing for this mode is identical to that for the MPU Priority scheme
