Another special SY6545 mode permits PH1/PH2 address multiplexing to be done internally, eliminating the need for external logic. Figure 11 is the circuit schematic for this implementation and Figure 12, the timings. This technique closely resembles the system depicted in Figure 4. Some highlights at this method follow:
Address multiplex switches are not required, since this is accomplished internal to the SY6545. The MPU address bus is not multiplexed, however. The internal Update Address Register is used instead. In this way, this mode resembles the previously mentioned Transparent Addressing mode.
The RAM is not addressed as a memory block, but as a single address. This derives from the fact that the address selected for updates or reads was previously stored in the CRTC. Table 6 summarizes the address decoding.
Note that this address decoding is identical to the other transparent mode. No data bus latches are required here, however, since the Update Address is on the MA lines each PH2 cycle and the operation does not have to wait for blanking times.
A significant difference between this mode and the normal PH1/PH2 interleave mode is that the address multiplexing in this mode is much slower. Figure 12 shows this. The result of this is that the MPU PH2 clock, normally used to gate the MPU R/!W signal to generate !WE for the RAM, may not be used for this purpose. If it is, a RAM write operation could inadvertently affect an undesired address location. This would happen when !WE went low (write) before the Update Address was driven onto the MA lines. To resolve this, it is necessary to generate a special gating clock (PH2') for RAM operations. PH2' is identical to PH2, except the leading edge is delayed about 150-200 nsec to compensate for the slow switching time of the MA lines.
The propagation delay of the MA lines, relative to PH2, results in a requirement for faster RAMs, since the write cycle (and read cycle, for the matter) is shortened by 150-200 nsec. Alternately, slower system timing may be used. In the example in Figures 11 and 12 all the times are doubled. In effect then, for this case, the display size was reduced from 80 x 24 to 40 x 24.
Figure 12 also illustrates the use of a clocked Cursor signal (clocked by the Shift Register !LD) .This is a simple technique to align the Cursor output from the CRTC with the Video dot pattern emanating from the Shift Register. This same technique is applicable to the Display Enable output.
Program Example to Load All SY6545 Internal Registers
A simple SY6500 family program to load all internal registers of the SY6545 is qiven in Figure 13. Typically, this routine is executed on power-up or System reset and rarely, if ever, otherwise. All methods outlined in this note may utilize the same routine, since the CRTC addressing is identical for all.
0000 *=$200 0200 ; REGISTER DATA TABLE 0200 31 .BYT 49 ; HOR TOT (N-1) 0201 28 .BYT 40 ; HOR DISP 0202 2D .BYT 45 ; HOR SYNC POS 0203 11 .BYT $11 ; HOR/VER SYNC WIDTHS 0204 1F .BYT 31 ; VER TOT (N-1) 0205 0B .BYT 11 ; VER TOT ADJ 0206 18 .BYT 24 ; VER DISP 0207 1C .BYT 28 ; VER SYNC POS 0208 B8 .BYT $B8 ; MODE CONTROL 0209 07 .BYT 07 ; SCAN LINES (N-1) 020A 00 .BYT $00 ; CUR START 020B 07 .BYT $07 ; CUR END 020C 00 .BYT $00 ; START - HI 020D 00 .BYT $00 ; START - LO 020E 00 .BYT $00 ; CUR - HI 020F 00 .BYT $00 ; CUR - LO 0210 00 .BYT $00 ; LIGHT PEN - HI 0211 00 .BYT $00 ; LIGHT PEN - LO 0212 00 .BYT $00 ; UA - HI 0213 00 .BYT $00 ; UA - LO 0214 AD6545=$4000 0214 ; 0214 ;----------- LOAD ALL 6545 REGISTERS ----------- 0214 ; 0214 *=$300 0300 A0 14 START1 LDY #$14 0302 A2 00 LDX #0 0304 8A BACK1 TXA 0305 8D 00 40 STA AD6545 0308 BD 00 02 LDA $200,X 030B 8D 01 40 STA AD6545+1 030E E8 INX 030F 88 DEY 0310 D0 F2 BNE BACK1