| GND | --- | -- | -- | -- | -- | -- | -- | -- | -- | -- | + | |||||||||||
| XTAL | --- | -- | -- | -- | -- | -- | -- | -- | -- | + | | | + | -- | -- | -- | -- | -- | -- | -- | -- | --> | RED |
| XTAL | --- | -- | -- | -- | -- | -- | -- | -- | + | | | | | | | + | -- | -- | -- | -- | -- | -- | -- | --> | GREEN |
| !RAS | <-- | -- | -- | -- | -- | -- | -- | + | | | | | | | | | | | + | -- | -- | -- | -- | -- | -- | --> | BLUE |
| !CAS | <-- | -- | -- | -- | -- | -- | + | | | | | | | | | | | | | | | + | -- | -- | -- | -- | -- | --> | COMP VID |
| E | <-- | -- | -- | -- | -- | + | | | | | | | | | | | | | | | | | | | + | -- | -- | -- | -- | <-> | RAM_D0 |
| Q | <-- | -- | -- | -- | + | | | | | | | | | | | | | | | | | | | | | | | + | -- | -- | -- | <-> | RAM_D1 |
| R/!W | --- | -- | -- | + | | | | | | | | | | | | | | | | | | | | | | | | | | | + | -- | -- | <-> | RAM_D2 |
| !RESET | --> | -- | + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + | -- | <-> | RAM_D3 |
| 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 68 | 67 | 66 | 65 | 64 | 63 | 62 | 61 | ||||||
| !WEN0 | --> | 10 | GIME ???? (PLCC68) |
60 | <-> | RAM_D4 | ||||||||||||||||
| !WEN1 | --> | 11 | 59 | <-> | RAM_D4 | |||||||||||||||||
| CPU_D0 | <-> | 12 | 58 | <-> | RAM_D6 | |||||||||||||||||
| CPU_D1 | <-> | 13 | 57 | <-> | RAM_D7 | |||||||||||||||||
| CPU_D2 | <-> | 14 | 56 | --> | !HSYNC | |||||||||||||||||
| CPU_D3 | <-> | 15 | 55 | --> | !VSYNC | |||||||||||||||||
| CPU_D4 | <-> | 16 | 54 | <-- | CPU_A15 | |||||||||||||||||
| CPU_D5 | <-> | 17 | 53 | <-- | CPU_A14 | |||||||||||||||||
| CPU_D6 | <-> | 18 | 52 | <-- | CPU_A13 | |||||||||||||||||
| CPU_D7 | <-> | 19 | 51 | <-- | CPU_A12 | |||||||||||||||||
| !FIRQ | --- | 20 | 50 | <-- | CPU_A11 | |||||||||||||||||
| !IRQ | --- | 21 | 49 | <-- | CPU_A10 | |||||||||||||||||
| !CART_INT | --- | 22 | 48 | <-- | CPU_A9 | |||||||||||||||||
| !KBD_INT | --- | 23 | 47 | <-- | CPU_A8 | |||||||||||||||||
| !RS232_INT | --- | 24 | 46 | <-- | CPU_A7 | |||||||||||||||||
| CPU_A0 | --> | 25 | 45 | <-- | CPU_A6 | |||||||||||||||||
| CPU_A1 | --> | 26 | 44 | <-- | CPU_A5 | |||||||||||||||||
| 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | ||||||
| CPU_A2 | --> | -- | + | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | + | -- | <-- | CPU_A4 |
| CPU_A3 | --> | -- | -- | + | | | | | | | | | | | | | | | | | | | | | | | | | | | + | -- | -- | --> | RAM_Z8 |
| S2 | <-- | -- | -- | -- | + | | | | | | | | | | | | | | | | | | | | | | | + | -- | -- | -- | --> | RAM_Z7 |
| S1 | <-- | -- | -- | -- | -- | + | | | | | | | | | | | | | | | | | | | + | -- | -- | -- | -- | --> | RAM_Z6 |
| S0 | <-- | -- | -- | -- | -- | -- | + | | | | | | | | | | | | | | | + | -- | -- | -- | -- | -- | --> | RAM_Z5 |
| RAM_Z0 | <-- | -- | -- | -- | -- | -- | -- | + | | | | | | | | | | | + | -- | -- | -- | -- | -- | -- | <-- | PULLUP |
| RAM_Z1 | <-- | -- | -- | -- | -- | -- | -- | -- | + | | | | | | | + | -- | -- | -- | -- | -- | -- | -- | --> | RAM_Z4 |
| RAM_Z2 | <-- | -- | -- | -- | -- | -- | -- | -- | -- | + | | | + | -- | -- | -- | -- | -- | -- | -- | -- | --> | RAM_Z3 |
| + | -- | -- | -- | -- | -- | -- | -- | -- | -- | --- | VCC | |||||||||||
| 61 | 63 | 65 | 67 | 01 | 03 | 05 | 07 | 09 | ||
| 60 | 62 | 64 | 66 | 68 | 02 | 04 | 06 | 08 | 11 | 10 |
| 58 | 59 | Bottom view of PLCC68 socket |
13 | 12 | ||||||
| 56 | 57 | 15 | 14 | |||||||
| 54 | 55 | 17 | 16 | |||||||
| 52 | 53 | 19 | 18 | |||||||
| 50 | 51 | 21 | 20 | |||||||
| 48 | 49 | 23 | 22 | |||||||
| 46 | 47 | 25 | 24 | |||||||
| 44 | 45 | 42 | 40 | 38 | 36 | 34 | 32 | 30 | 28 | 26 |
| 43 | 41 | 39 | 37 | 35 | 33 | 31 | 29 | 27 | ||
WEnx = Write Enables for Banks 0 and 1 RAM
| S2 | S1 | S0 | Address select code -> 74LS138 | |
| 0 | 0 | 0 | 0 | ROM |
| 0 | 0 | 1 | 1 | CTS |
| 0 | 1 | 0 | 2 | FF0X, FF2X |
| 0 | 1 | 1 | 3 | FF1X, FF3X |
| 1 | 0 | 0 | 4 | int SCS |
| 1 | 0 | 1 | 5 | n/a |
| 1 | 1 | 0 | 6 | norm SCS |
| 1 | 1 | 1 | 7 | ??ram?? |
CN6 - Gnd, +5, D1, D0, D2, D3, D6, D7, D5, D4, WEn1, Gnd CN5 - Gnd, D2, D3, D1, WEn0, D0, CAS, D6, D5, D4, D7, Gnd CN2 - Gnd, RAS, Z0, Z1 , Z2, Z3, Z4, Z5, Z6, Z7, Z8, Gnd
Note: Since a lot of this is by a QUICK observation, CHECK
first if using!
Though as far as the CN's go, even if I have messed up all but
the CAS, RAS, WEn's, and +5, you could connect the extra RAM Dx
and Zx pins in parallel toeach bank in any order. The RAM's don't
care.
CN6 and CN5 data lines go to separate 256K banks, of course.
This information was gathered by Kevin K. Darling.
NOTE !!
This is a text for you to use to study the capabilities of the
CoCo-3.
Some minor parts may be in error (??). Insiders should clue us in
on these.
Purpose of release is to show some of the extra thought in the
machine.
In NO way should it be construed as an "official map".
Now have fun! -- Kevin
* Many Thanks from All of Us to the Contributors who shall remain UnKnown! *
SYSTEM MEMORY MAP:
RAM 00000 - 7FFFF (512K bytes) ROM 78000 - 7FEFF when enabled I/O XFF00 - XFFFF I/O space and GIME regs
64K PROCESS MAP:
RAM 0000 - FEFF (possible vector page FEXX) I/O FF00 - FFFF (appears in all pages)
Note: the Vector Page RAM at 7FE00 - 7FEFF (when enabled), will appear instead of the RAM or ROM at XFE00 - XFEFF. (see FF90 Bit 3)
| XFF00-0X | PIA0 (not fully decoded) |
| XFF10-1F | Reserved |
| XFF20-2X | PIA1 (not fully decoded) |
| XFF30-3F | Reserved |
| XFF40-5F | SCS see note below |
| XFF60-7F | Undecoded (for current peripherals) |
| XFF80-8F | Reserved |
Note: IF MC2=0, then XFF50-5F is SCS, and XFF40-4F will be internal to CoCo.
FF90 INITIALIZATION REGISTER 0
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||
| MC1,0 | ROM mapping | ||||||||
| 0 | X | 16K internal, 16K external | |||||||
| 1 | 0 | 32K internal | |||||||
| 1 | 1 | 32K external | |||||||
| 1 | MC2 | Standard SCS | |||||||
| 1 | MC3 | Vector page RAM at FEXX enabled | |||||||
| 1 | FEN | GIME FIRQ " " | |||||||
| 1 | IEN | GIME IRQ output enabled to CPU | |||||||
| 1 | M/P | MMU enabled | |||||||
| 1 | CoCo Bit | Color Computer 1/2 Compatible | |||||||
CoCo bit set = MMU disabled, Video address from SAM, RGB/Comp Palettes => CC2.
FF90 INITIALIZATION REGISTER 1
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||
| TR | MMU Task Register Select (0/1 - see FFA0-AF) | ||||||||
| 1 | TINS | Timer INput Clock Select: 0= 70 nsec, 1= 63 usec | |||||||
| 1 | M/P | 0=64K chips, 1 = 256K chips | |||||||
FF92 IRQENR Interrupt Request
Enable Register (IRQ)
FF93 FIRQENR Fast Interrupt Request Enable Reg (FIRQ)
(Note that the equivalent interrupt output enable bit must be
set in FF90.)
Both registers use the following bits to enable/disable device
interrupts:
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||
| 1 | EI0 | Cartridge (CART) | |||||||
| 1 | EI1 | Keyboard | |||||||
| 1 | EI2 | Serial data input | |||||||
| 1 | VBORD | Vertical border | |||||||
| 1 | HBORD | Horizontal border | |||||||
| 1 | TMR | Timer | |||||||
I have no idea if both IRQ & FIRQ can be enabled for a device at same time.
| FF94 | Timer MSB | Write here to start timer. |
| FF95 | Timer LSB | Load starts timer countdown. Interrupts at zero,
reloads count & continues. Must turn timer interrupt enable off/on again to reset timer IRQ/FIRQ. |
| FF96 | Reserved | |
| FF97 | Reserved |
FF98 Alpha/graphics Video modes, and lines per row.
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | ||
| LPR2,1,0 | Lines per character row: | ||||||||
| 0 | 0 | 0 | 1 line/row | ||||||
| 0 | 0 | 1 | 2 | ||||||
| 0 | 1 | 0 | 3 | ||||||
| 0 | 1 | 1 | 8 | ||||||
| 1 | 0 | 0 | 9 | ||||||
| 1 | 0 | 1 | 10 | ||||||
| 1 | 1 | 0 | 11 (??) | ||||||
| 1 | 1 | 1 | 12 (??) | ||||||
| 0 | |||||||||
| 0 | H50 | 50hz vs 60hz bit | |||||||
| 0 | MOCH | MOnoCHrome bit (composite video output) (1=mono) | |||||||
| 0 | DESCEN | 1= extra DESCender ENable | |||||||
| 0 | |||||||||
| 0 | 0 is alphanumeric, 1= bit plane (graphics) | ||||||||
FF99 VIDEO RESOLUTION REGISTER
Text: CoCo Bit= 0 and FF98 bit7=0. CRES0 = 1 for: attribute bytes are used.
D5,4,3 = HR2,1,0: Horizontal Resolution D1,0 = CRES1,0: Color RESolution bits
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |||
| X | Colours | |||||||||
| 0 | 1 | 0 | 0 | 0 | 256 | 2 | GRAPHICS
MODES |
|||
| 0 | 1 | 1 | 320 | |||||||
| 1 | 0 | 0 | 512 | |||||||
| 1 | 0 | 1 | 640 | |||||||
| 1 | 0 | 0 | 0 | 1 | 256 | 4 | ||||
| 1 | 0 | 1 | 320 | |||||||
| 1 | 1 | 0 | 512 | |||||||
| 1 | 1 | 1 | 640 | |||||||
| 1 | 0 | 1 | 1 | 0 | 160 | 16 | ||||
| 1 | 1 | 0 | 256 | |||||||
| 1 | 1 | 1 | 320 | |||||||
| 0 | X | 0 | 32 | TEXT MODES: |
||||||
| 0 | X | 1 | 40 | |||||||
| 1 | X | 0 | 64 | |||||||
| 1 | X | 1 | 80 | |||||||
| 0 | 0 | 192 | ||||||||
| 0 | 1 | 200 | ||||||||
| 1 | 0 | 210 | ||||||||
| 1 | 1 | 225 | ||||||||
Other combo's are possible, but not supported.
Old SAM modes work if CC Bit set. HR and CRES are Don't Care
in SAM mode.
Note the correspondence of HR2 HR0 to the text mode's bytes/line.
Also that CRES bits shifted left one = number of colors. --Ke
X Colors HR2 HR1 HR0 CRES1 CRES0
640 2 - 1 0 1 0 0
320 2 - 0 1 1 0 0
256 2 - 0 1 0 0 0
512 2 - 1 0 0 0 0
256 4 - 1 0 0 0 1
512 4 - 1 1 0 0 1
640 4 - 1 1 1 0 1
320 4 - 1 0 1 0 1
320 16 - 1 1 1 1 0
160 16 - 1 0 1 1 0
256 16 - 1 1 0 1 0
| FF9A | Border Palette Register RGBRGB (XX00 0000 = CoCo 1/2 compatible) |
| FF9B | Reserved |
| FF9C | Vertical Fine Scroll |
| FF9D | Screen Start Address Register 1 (bits 18-11) |
| FF9E | Screen Start Address Register 0 (bits 10-3) |
| FF9F | Horizontal Offset Register |
| Bit 7 = horizontal offset enable bit = 128 char width
always Bit 6 = X6 ... offset count (0-127) Bit 0 = X0 If Bit 7 set & in Text mode, then there are 128 chars (only 80 seen)/line. This allows an offset to be specified into a virtual 128 char/line screen, useful for horizontal hardware scrolling on wide text or spreadsheets. |
MEMORY MANAGEMENT UNIT (MMU)
| FFA0-A7 | Task #0 DAT map (8K block numbers in the 64K map) |
| FFA8-AF | Task #1 DAT map (Task map in use chosen by FF91 Bit 0) |
Each register has 6 bits into which is stored the block number
0-63 ($00-$3F) of the Physical 8K RAM block (out of 512K) that
you wish to appear at the CPU Logical address corresponding to
that register.
Also can be shown this way: the 6 register bits, when the Logical
Address in the range of that register, will become the new
Physical RAM address bits 18 17 16 15 14 13
| MMU Register: | CPU | ||
| Task0 | Task1 | Logical Address | Block# |
| FFA0 | FFA8 | 0000 - 1FFF | 0 |
| FFA1 | FFA9 | 2000 - 3FFF | 1 |
| FFA2 | FFAA | 4000 - 5FFF | 2 |
| FFA3 | FFAB | 6000 - 7FFF | 3 |
| FFA4 | FFAC | 8000 - 9FFF | 4 |
| FFA5 | FFAD | A000 - BFFF | 5 |
| FFA6 | FFAE | C000 - DFFF | 6 |
| FFA7 | FFAF | E000 - FDFF | 7 |
Ex: You wish to access Physical RAM address $35001. That Address is:
| 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 3 | 5 | 0 | 0 | 1 | ||||||||||||||
| 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Taking address bits 18-13, we have: 0 1 1 0 1 0, or $1A, or 26. This is the physical RAM block number, out of the 64 (0-63) available in a 512K machine.
Now, let's say you'd like to have that block appear to the CPU at Logical Block 0 (0000-1FFF in the CPU's 64K memory map).
You would store the Physical Block Number ($1A) in either of the two Task Map registers that are used for Logical Block 0 (FFA0 or FFA8). Unless your program that is doing this is in the Vector RAM at FEXX (set MC3 so ALWAYS there), you would want to use your current Task Map register set. If the TR bit at FF91 was 0, then you'd use MMU register FFA0 for the $1A data byte.
To find the address within the block, use Address Bits 12-0
plus the Logical base address (which in this case is $0000):
Now you could read/write address $1001, which would actually be
$35001.
FFB0-BF Color Palette Registers
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
| I1 | I0 | P3 | P2 | P1 | P0 | CMP: Intensity and Phase (16 colors x 4 shades) | ||
| R1 | G1 | B1 | R0 | G0 | B0 | RGB: Red Green Blue (64 RGB combo's) |
When CoCo Bit is set, and palette registers preloaded with certain default values (ask, if you need these), both the RGB and CMP outputs appear the same color, supposedly.
40/80 Column Text Screen Bytes are Even=char, Odd=attribute,
in memory.
Characters selected from 128 ASCII. NO text graphics-chars.
Char Attributes- 8 bits... F U T T T B B B
Flashing, Underline, Text foregrnd, Backgrnd colors 0-7.
FFC0-DF SAM : same as before (mostly compatible Write-Only Switches) FFD8 = CPU .895 MHz (no address-dependent speed) FFD9 = 1.79 MHz FFDE = Map RAM/ROM (RAM accesses use MMU translations) FFDF = all RAM
This is an addendum to GIME.TXT elsewhere in this Library.
Meant for all, but as FREE distribution only.
Please address info to Kevin Darling 73117,1375 for next update.
Let's keep the info flowing! The SIG purpose is to share
knowledge.
Thanks to Greg Law and his friend Dennis W. for much register
info.
Thanks to Others and Marsha (for my magnifier) on many of the
pin-outs.
$FF91 - Bit 5, Timer Input Select. Looks like 0=slower speed, instead. Haven't had time to put a scope on it to check actual clocks, yet.
$FF92-3 - Interrupt Request Regs: You can also read these regs to see if there is a LOW on an interrupt input pin. If you have both the IRQ and FIRQ for the same device enabled, you read a Set bit on both regs if that input is low.
For example, if you set $FF02=0 and $FF92=2, then as long as a key is held down, you will read back Bit 1 as Set.
The keyboard interrupt input is generated by simply AND'ing all the matrix pins read back at $FF00. Therefore, you could select the key columns you wished to get by setting the appropriate bits at $FF02 to zero. Pressing the key drops the associated $FF00 line to zero, causing the AND output to go low to the GIME. Setting $FF02 to all Ones would mean only the Joystick Fire buttons would generate interrupts.
$FF94-95 - Storing a $00 at $FF94 seems to stop the timer. Also, apparently each time it passes thru zero, the $FF92/93 bit is set without having to re-enable that Int Request.
$FF98 - Bit 5 is the artifact color shift bit. Change it to flip Pmode 4 colors. A One is what is put there if you hold down the F1 key on reset. POKE &HFF98,&H13 from Basic if your colors artifact the wrong way for you.
$FF9F - Horz Offset Reg. If you set Bit 7 and you're in Gfx mode, you can scroll across a 128 byte picture. To use this, of course, you'd have to write your own gfx routines. On my machine, tho, an offset of more than about 5 crashes.
$FFB0-BF - As I originally had, and we all know by now, FFB0-B7 are used for the text mode char background colors, and FFB8-BF for char foreground colors, in addition to their other gfx use.
The 68B09E address lines finally have pullup resistors on them. Probably put in for the 2MHz mode, they also help cure a little-known CoCo phantom: since during disk access, the Halt line tri-states the address, data, and R/W lines, some old CoCo's would float those lines right into writing junk in memory. Now $FFFF would be presented to the system bus instead.
Since the GIME catches the old VDG mode info formerly written to the PIA at $FF22, those four now-unconnected lines (PB4-7 on the 6821) might have some use for us.
Also, Pin 10 of the RGB connector is tied to PB3 on the same PIA. Shades of the Atari ST. Could possibly be used to detect type of monitor attached, if we like.
Data read back from RAM must go through a buffer, the GIME, and another buffer. Amazing that it works at 2 MHz.
In case you didn't catch the hint from GIME.TXT on FF90 Bit 2, the option of an internal SCS select opens up the possibility of a CoCo-4 with a built-in disk controller.
General Info:
Data is written to the RAM by byte through IC10 or IC11,
selected by WEn 0 or 1.
(write enable 0 = even addresses, write enable 1 = odd addresses)
Two bank RAM data is read back to the GIME thru IC12 &
IC13, byte at a time.
The CPU can then get it from the GIME by byte.
IC 10, 11, 12 = 74LS244 buffer. IC13 = 74LS374 latch clocked by CAS* rise.
RAM Read --> IC12 --> GIME enabled by CAS low. (read first)
RAM Read --> IC13 --> GIME enabled by CAS hi. (latched & read)
Test Points:
TP 2 = E TP 3 = Q TP 4 = RAS TP 5 = CAS TP 6 = Composite Video TP 8 = Red TP 9 = Green TP10 = Blue