MV1815

SINGLE CHIP TELETEXT DECODER FOR 625 LINE OPERATION

The MV1815 is an advanced CMOS single chip Teletext decoder for 625 line World System Teletext. The MV1815 has an on-chip data slicer circuit, dual page acquisition circuits, and direct memory addressing, which allow a low cost Teletext decoder to be built with a minimum number of additional components.

FEATURES

Chip Data Slicing.
Up to 254 Display Pages Stored, using Low Cost 150 ns DRAMs.
Low External Component Count.
I2C Bus for Low Cost Interfacing.
Multi-language Capability for Fourteen European Languages.
Special Parity Inhibit Feature for Table Of Pages 8-bit Data.
Non-display Packets Stored for Linked Page Operation, Video Programming, etc.
High Resolution Characters Typically 12 Dots Wide on a 15 by 10 Matrix.
Accepts all Non-display Packets.
On-chip Video Switch.
Advanced CMOS Technology gives Low Power Dissipation and High Reliability.

GEC PLESSEY SEMICONDUCTORS

Fig.1 Pin connections - top view

`GND`	`---`	`1`	`--MV1815--`	`40`	`---`	`VDD`
`XTO`	`<--`	`2`		`39`	`-->`	`!EVENT`
`!XTI`	`-->`	`3`		`38`	`<->`	`SDA`
`A9`	`<--`	`4`		`37`	`<->`	`SCL`
`A7`	`<--`	`5`		`36`	`-->`	`A1`
`A5`	`-->`	`6`		`35`	`-->`	`A2`
`A4`	`<->`	`7`		`34`	`-->`	`A0`
`A3`	`<->`	`8`		`33`	`-->`	`!RAS`
`A6`	`<->`	`9`		`32`	`-->`	`!CWR`
`D1`	`<->`	`10`		`31`	`-->`	`!CAS`
`D0`	`<->`	`11`		`30`	`-->`	`TEST/EVEN`
`A8`	`<--`	`12`		`29`	`<--`	`VSI`
`!RESET`	`-->`	`13`		`28`	`-->`	`CSO`
`SYNC_I/O`	`<->`	`14`		`27`	`-->`	`ONH`
`DATA_I/O`	`<->`	`15`		`26`	`-->`	`BLUE`
`EXT/!INT`	`-->`	`16`		`25`	`-->`	`GREEN`
`BLC`	`---`	`17`		`24`	`-->`	`RED`
`WLC`	`---`	`18`		`23`	`-->`	`BLANK`
`VIDEO_IN`	`-->`	`19`		`22`	`---`	`TCR`
`GND`	`---`	`20`		`21`	`---`	`VDD`

GEC PLESSEY SEMICONDUCTORS

Fig.2. MV1815 block diagram

Table 1. MV1815 system specification

Section

Specification

Data Acquisition Logic

Line standard

625 Lines 50 Fields: second

Teletext data rate

6.9375 Mbits/sec +/- 25 ppm

Data line content

360 bits as 45 bytes of 8 bits each

TV lines used VBI

Lines 6 to 22 and 318 to 335

TV lines used full field

All TV Lines

Packets accepted

X/0 to X/25, X/26, X/27, X/28, X/29, 8/30 (all formats), X/31

Page numbers

000 to 0FF

Page subcodes

0000 to 3F7F

Display Logic

Characters per row

40, occupying 43.24 us of the 52 us display time

Teletext rows displayed

0 to 23 with 24 and 25 software programmable

TV lines used

Rows displayed	TV
Rows displayed	Start	Finish
24	48	287
25 or 26	38	297

Character definition

15 x 10 dot matrix

Character sets

English, German, Swedish, Italian, French, Spanish, Czechoslovakian, Polish, Romanian, Hungarian, Turkish Danish, Serbo-Croat, ASCII.

Spacing control characters

Standard Level One Range

Data boxing into picture

Page Number - Row 0 characters 1 to 8
Page Header - Row 0 characters 9 to 32
Clock Time - Row 0 characters 33 to 40
Rows 24 and 25

Displayable page stores

Up to 254 pages, each of 1 Kbyte depending on size of the DRAM being used

Display options

Mix of text foreground and picture background
Three part magnify - display:

rows 0 to 11 double height
rows 6 to 17 double height
rows 12 to 23 double height

Boxing of Newsflash and Subtitles into picture
Boxing of picture into text

Dynamic RAM Control Logic

Memory configuration

All sizes Page or nibble mode types
254 pages – 2 off 1M x 1 or 1 off 1M x 4
62 pages - 2 off 256K x 1 or 1 off 256K x 4
14 pages – 2 off 64K x 1 or 1 off 64K x 4

Maximum access time (t_RAC)

150 ns

Refresh period for complete memory

2.048 ms. Refresh occurs during the line flyback period.
Contents of any memory location may be accessed by
the microprocessor via the I2C Bus interface.

I2C Bus Interface

Standard implementation of a slave transmitter / receiver Control of the MV1815 is via 32 on - chip registers.

I2C Bus Address

0010 001 R/!W

Table 2. Pin Description

Symbol	Pin No	Pin Name and Description
GND	1,20	Ground, both pins must be connected
XTO	2	Crystal out 27.75MHz fundamental crystal with an on-chip 1MB bias resistor to XTI
!XTI	3	Crystal input
A9,A7,A5,A4, A3, A6,A8, A0,A2,A1	4-9 12,34, 35,36	DRAM address outputs
D1,D0	10,11	DRAM data lines. Internal 100k pull-up resistors are included.
!RESET	13	Active low reset input. Includes 100k pull-up resistor.
SYNC I/0	14	Sliced sync input /output.
DATA I/0	15	Teletext data input /output.
EXT/!INT	16	Control pin for SYNC and DATA I/0. Includes 100k pull-down resistor. When low or not connected internal SYNC and DATA are used, pins 14 &15 are outputs. When high supply SYNC and DATA from an external source, pins 14 & 15 are input.
BLC	17	Black level capacitor.
WLC	18	White level capacitor.
VIDEO IN	19	Input for composite video signal with negative going SYNCs.
VDD	21, 40	+5V Supply. Both pins must be connected.
TCR	22	Time constant resistor controlling discharge rate of black and white level capacitor voltages.
BLANK	23	Blanking output, high power push-pull driver.
RED	24	Red output, high power push-pull tri-state driver.
GREEN	25	Green output, high power push-pull tri-state driver.
BLUE	26	Blue output, high power push-pull tri-state driver.
ONH	27	On hours indicator. When high CSO is locked to Video In. When low CSO is not locked.
CSO	28	Generated composite sync output during text, video input is switched through to CSO during modes that contain picture content. See Fig. 6:
VSI	29	Video switch input.
TEST/EVEN	30	Test input is used for factory testing. EVEN output is enabled by bits IOE and EOE in SYNCSW register. If EVEN output is not used, the pin should be left open-circuit. A 100k pull-down resistor is included.
!CAS	31	DRAM column address strobe
!WR	32	DRAM read / write signal.
!RAS	33	DRAM row address strobe.
SCL	37	I2C bus serial clock.
SDA	38	I2C bus bi-directional data port
!EVENT	39	Active low open drain output interrupt signal to microprocessor.

Crystal specification

Parallel resonant fundamental frequency:
27.750000MHz. AT cut.
Tolerance at 20ºC +/- 20ppm.
Tolerance at -10ºC to 60ºC +/- 50ppm.
Tolerance overall +/- 100ppm.
Nominal load capacitance 20pF
Equivalent series resistance < 20R

A variable capacitor is provided internally on pin XTI and controlled by a phase locked loop to provide exact trimming of the frequency.

This will provide compensation for temperature variation and crystal ageing.

Table 3. MV1815 register details

Address

Reg.
name

R/W

Reset
state
Hex

Dec

Hex

RADD

A17

A16

IAI

RA4

RA3

RA2

RA1

RA0

ACONA

ACQ

MGC

PBC

PAC

SDC

SCC

SBC

SAC

STORA

STA7

STA6

STA5

STA4

STA3

STA2

STA1

STA0

PGS1A

SCS3

SCS2

SCS1

SCS0

SAS3

SAS2

SAS1

SAS0

PGS2A

MS2

MS1

MS0

SDS1

SDS0

SBS2

SBS1

SBS0

PGS3A

PBS3

PBS2

PBS1

PBS0

PAS3

PAS2

PAS1

PAS0

ACONB

HLD (bar)

MGC

PBC

PAC

SDC

SCC

SBC

SAC

STORB

STB7

STB6

STB5

STB4

STB3

STB2

STB1

STB0

PGS1B

SCS3

SCS2

SCS1

SCS0

SAS3

SAS2

SAS1

SAS0

PGS2B

MS2

MS1

MS0

SDS1

SDS0

SBS2

SBS1

SBS0

PGS3B

PBS3

PBS2

PBS1

PBS0

PAS3

PAS2

PAS1

PAS0

RECON

WIO

WI24

WI25

PINB

PINA

CDB

CDA

DISCON1

INV

RLH

DSB

CLS

CUR

BLC

LS3

UDI

DISCON2

LSO

LS1

LS2

MGS

IHD

SPH

BX1

BX0

DISCON3

TXT

MIX

INT

REV

UDK

SPOS

ST2

ST1

DISCON4

BXP

BXH

BXT

BXS

DHT

DHB

SG2

SG1

HADD

A15

A14

A13

A12

A11

A10

LADD

WDATA

WD7

WD6

WD5

WD4

WD3

WD2

WD1

WD0

SCROLL

WI29

CRL

SRA4

SRA3

SRA2

SRA1

SRA0

SYNCSW

ESS

IOE

EOE

SEN

SVS

EVENTA

NPR

VHR

830A

X/29

X/28

X/27

X/26

EVENTB

NPR

VHR

830B

X/29

X/28

X/27

X/26

CBITS

C14

C13

C12

C11

C10

PGR1A

SCR3

SCR2

SCR1

SCR0

SAR3

SAR2

SAR1

SAR0

PGR2A

MR2

MR1

MR0

SDR1

SDR0

SBH2

SBR1

SBR0

PGR3A

PBR3

PBR2

PBR1

PBR0

PAR3

PAR2

PAR1

PAR0

CBITSB

C14

C13

C12

C11

C10

PGR1A

SCR3

SCR2

SCR1

SCR0

SAR3

SAR2

SAR1

SAR0

PGR2A

MR2

MR1

MR0

SDR1

SDR0

SBH2

SBR1

SBR0

PGR3A

PBR3

PBR2

PBR1

PBR0

PAR3

PAR2

PAR1

PAR0

HAMMC

HC7

HC6

HC5

HC4

HC3

HC2

HC1

HC0

RDATA

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

NOTE: Write register addresses 18 and 21-31 (12 and 15-1F HEX) are reserved for future development and should not be used.

WRITE REGISTERS

RADD (W)	
A16/A17 Memory quadrant select.	
IAI Inhibit auto increment.
RA$ Register address ($ = 0 to 4).

ACON A/B (W 0 & 5)
ACQ Acquisition on.
MGC Magazine compare.
PAC Page units compare.
PBC Page tens compare.
SAC Page subcode compare digit A.
SBC Page subcode compare digit B.
SCC Page subcode compare digit C.
SDC Page subcode compare digit D.
HLD(bar) Not hold display acquisition circuit.

STOR A/B (W 1 & 6)
STA$ Store number for acquisition A ($ = 0 to 7).
STB$ Store number for acquisition B ($ = 0 to 7).

PGS /1 /2 /3 A/B (W 2,3,4 & 7,8,9)
SAS$ Sub-Code digit A ($ = 0 to 3) select.
SBS$ Sub-Code digit B ($ = 0 to 2) select.
SCS$ Sub-Code digit C ($ = 0 to 3) select.
SDS$ Sub-Code digit D ($ = 0 or 1) select.
PAS$ Page number (units) ($ = 0 to 3) select.
PBS$ Page number (tens) ($ = 0 to 3) select.
MS$  Magazine number ($=0 to 2) select.

RECON (W 10)
WIO  Write inhibit of packet 0.
WI24 Write inhibit of packet 24.
WI25 Write inhibit of packet 25.
PINB Parity check inhibit acquisition circuit B.
PINA Parity check inhibit acquisition circuit A.
FF   Full field Teletext.
CDA  Clear store disable acquisition circuit A.
CDB  Clear store disable acquisition circuit B.

DISCON1 (W11)
INV Invert display.
RLH Roll headers.
DSB Display acquisition circuit B (A if zero).
CLS Clear current display store
CUR Cursor enable
BLC Block cursor
LS3 Language group select
UDI Display update indicator.

DISCON2 (W 12)
LS$ Language select ($ = 0 to 2).
MGS Magazine serial.
IHD Inhibit display, rows 2 to 26 disabled.
SPH Suppress header.
BX$ Box control bits ($ = 0 or 1)

DISCON3 (W 13)	
TXT Text / not picture
MIX Mix text and picture
INT Display text in interlace mode (see Figure 6).
REV Reveal hidden text
UDK Update key, rows 1 to 26 disabled.
SPOS Status line position
ST2 Display Status line 2 (row 26).
ST1 Display Status line 1 (row 25).

DISCON4 (W 14)
BXP Box page number.
BXH Box header.
BXS Box status rows.
DHT Double height top half.
DHB Double height bottom half.
SGS Separated graphics control bits ($ = 0 or 1).

HADD and LADD (W 15 & 16)
A$   Memory address ($ = 0 to 15).

WDATA	(W 17)
WD$  Data to be wntten to memory ($ = 0 to 7).

SCROLL (W19)
WI29 Write inhibit of packet 29
MV   Majority vote on framing code
CRL  Cursor lock at last HADD, LADD setting
SRA$ Scroll display row up ($ = 0 to 23 only)

SYNCSW	(W 20)
ESS External sync source
I0E Interlace output enable
EOE EVEN output enable
SEN Select enable - SVS bit
SVS Select VSI as sync source

READ REGISTERS

EVENT A/B (R 0 & 1 )
NPR  New page received.
VHR  Valid header received.
830$ Packet 30 received acquisition $ ($ = A or B).
X/29 Packet 29 received.
X/28 Packet 28 received.
X/27 Packet 27 received.
X/26 Packet 26 received.
C8   Update Indicator

CBITS A/B (R 2 & 6)
C14 Language select bit
C13 Language select bit
C12 Language select bit.
C11 Magazine serial.
C10 Inhibit display.
C7  Suppress header.
C6  Sub-title
C5  Newsflash

PGR 1 /2 /3 A/B (R 3,4,5 & 7,8,9)
SARS Sub-code digit A ($ = 0 to 3) received
SBB$ Sub-code digit B ($ = 0 to 2) received.
SCR$ Sub-code digit C ($ = 0 to 3) received.
SDRS Sub-code digit D ($ = 0 or 1) received.
PAR$ Page number (units) ($ = 0 to 3) received.
PBR$ Page number (tens) ($ = 0 to 3) received
MR$  Magazine number ($ = 0 to 2) received.

HAMMC (R 10)
HC$  Hamming counter (5 = 0 to 7)

RDATA (R 17)
RD$  Data read from memory ($ = 0 to 7).

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated)
Tamb = 0 to 70ºC, VDD = 5V+ 10%

Characteristic	Pin	Min	Typ	Max	Units	Conditions
Supply Voltage	21 & 40	4.5	5.0	5.5	V	!XTI = 27.75MHz All outputs open circuit
Supply Current			25		mA	!XTI = 27.75MHz All outputs open circuit
Supply Current			15		mA	!XTI = 0 Hz All outputs open circuit
Video Input,VSI	19 & 29
Voltage amplitude		0.8		3.0		Vp-p Bottom of Sync to White (p-p)
Source impedance				250	R
TCR input	22
External resistance		5	10	200	k	Connected to VDD
BLC and WLC	17 & 18
Capacitor value			10		nF	Connected to GND
Capacitor tolerance		-10		+ 10	%
Effective series resistance				.5	R	1MHz
Sync I/0	14					100k (nominal) pull-up resistor
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
Input voltage low		0		1.0	V
Input voltage high		Vpp-1.0		VDD	V
Input current low		-22	-50	-220	uA	VIN = VSS
Input current high		-30		+30	uA	VIN = VDD
Data I/0	15			5	R	No pull-up resistor
Output voltage high		2.4		4.5	V	IOH = -1.2mA
Output voltage low			0.2	0.4	V	lOL = 2.4mA
Input voltage low		0		1.0	V
Input voltage high		VDD-1.0		VDD	V
Input current		-30		+30	uA	VIN = VDD or VSS
EXT/INT (note 1)	16					100k (nom) pull-down resistor
Input current low		-10		+ 10	uA	VIN = VSS
Input current high		22	50	220	uA	VIN = VDD
!XTI (note 1)	3					1M (nom) resistor to XTO
Input current low		-0.5	-5.0	-20	uA	-0.3 < VIN < VIL max
Input current high		0.5	5.0	20	uA	VIH min < VIN< (VDD+ 0.3)
XTO output	2					See note 2
Output voltage high		VDD-1.0	4.5		V	IOH = - 1.0 mA
Output voltage low			0.2	0.4	V	IOL = 2.0 mA
Frequency			27.750		MHz	+/- 100 ppm
On Hour Indicator ONH	27
Output voltage high		VDD-1.0	4.5		V	IOH = - 1.2 mA
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
I2C Bus SCL, SDA I/Ps	37, 38					100k (nom) pull-up resistor
Input voltage low		0		1.5	V
Input voltage high		3.5		VDD	V
Output voltage low		0	0.1	0.4	V	IOL = 3.0 mA
SCL clock frequency	37		100	1000	kHz
Red, Green, Blue	24,25,76
Output voltage high		VDD-1.0	4.5		V	IOH = - 12 mA
Output voltage low			0.2	0.4	V	IOL = 24 mA
Tri-state output leakage current		-60		60	uA	VOH = VSS or VDD
EVENT	39					100k (nom} pull-up resistor
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
Blank	23
Output voltage high		VDD-1.0	4.5		V	IOH = - 12 mA
Output voltage low			0.2	0.4	V	IOL = 24 mA
CSO	28					With typical load of 360R
Output voltage swing			0.5		Vpp	Text mode only, see note 3.
TEST/EVEN	30					100k (nom) pull-down resistor
Output voltage high		VDD-1.0	4.5		V	IOH = - 1.2 mA
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
Input voltage low		0		1.0	V
Input voltage high		VDD-1.0		VDD	V
Input current low		-30		+30	uA	VIN = VSS
Input current high		22	50	220	uA	VIN = VDD
Memory Interface						100k (nom) pull-down resistor
Data D0,D1	11,10
Output voltage high		VDD-1.0	4.5		V	IOH = - 1.2 mA
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
Input voltage low		0		1.0	V
Input voltage high		VDD-1.0		VDD	V
Input current low		-22	-50	-220	uA	VIN = VSS
Input current high		-30		+30	uA	VIN = VDD
Address A0-A9, !RAS, !CAS, !WR	see Fig. 1					100k (nom) pull-down resistor
Output voltage high		VDD-1.0	4.5		V	IOH = - 1.2 mA
Output voltage low			0.2	0.4	V	IOL = 2.4 mA
!RESET (Schmitt input)	13					100k (nom) pull-down resistor
Input voltage low		0		1.0	V
Input voltage high		VDD-1.0		VDD	V
Input current low		-22	-50	-220	uA	VIN = VSS
Input current high		-10		+10	uA	VIN = VDD
Hysteresis voltage		0.8			V	(Rising threshold) - (falling threshold) voltages

ABSOLUTE MAXIMUM RATINGS

Supply voltage. VDD	-0.3V to +7.0V
All inputs	-0.3V to VDD+0.3V
Operating temperature	-40ºC to +85ºC
Storage temperature	-65ºC to+ 150ºC

NOTES

Input voltage low and Input voltage high for these inputs are as specified for Data I/O
When !RESET is held low, A9 (pin 4) will output fosc/2.
If required, adjust capacitor on XTO for a frequency of 13.875 MHz.
CSO output voltage when in Picture or Mix mode will depend on size of video signal applied to VSI pin 29,
together with attenuation due to internal transmission switch (60R nom) and external load on pin 28.
In these states the video signai at pin 29 is switched straight through to pin 28.

Fig 5. Store 0 memory organisation

Packet 8/30 designation codes 0,1,4,5,8,9,C and D are written to store 0.

First byte Absolute Address HEX					Last byte Absolute Address HEX
		Page Number Addr 0-7	Time Addr 8-F	Packet X/31 Addr 10-17
00018	ACQUISITION A PACKETS X/26, X/27 OR X/28 IN ANY ORDER UP TO 23 PACKETS				0003F
00040
00068
00090
000B8
000E0
00108
00130
00158
00180
001A8
001D0
001F8
00220
00248
00270
00298
002C0
002E8
00310
00338
00360
00388
003B0	PACKET 8/29
003DB	PACKET 8/30				003FF

NOTE

Store 1 is organised similarly except that it accepts acquisition circuit B packets X/26, etc. The starting address is 00400 (HEX) and bytes 00400 to 00417 (HEX) are not used by the MVI815. All addresses shown in fig 5 add 00400 (HEX). Packet 8/30 designation codes 2, 3, 6,7, A, B, E and F are written to store 1.

Fig 6a. Composite Sync output (interlaced) and EVEN output

Fig 6b. Composite Sync output (non-interlaced) and EVEN output

Fig 7. Timing of display window for RGB outputs related to composite sync output

Table 4. Control Characters, Primary (English) Character set G0
and Mosaic Graphics set G1

[not reproduced here because character set and control codes already well known]